SAA7118 Datasheet, PDF (47/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
8.4 Scaler
The High Performance video Scaler (HPS) is based on the
system as implemented in the SAA7140, but with some
aspects enhanced. Vertical upsampling is supported and
the processing pipeline buffer capacity is enhanced, to
allow more flexible video stream timing at the image port,
discontinuous transfers, and handshake. The internal data
flow from block to block is discontinuous dynamically, due
to the scaling process itself.
The flow is controlled by internal data valid and data
request flags (internal handshake signalling) between the
sub-blocks; therefore the entire scaler acts as a pipeline
buffer. Depending on the actually programmed scaling
parameters the effective buffer can exceed to an entire
line. The access/bandwidth requirements to the VGA
frame buffer are reduced significantly.
The high performance video scaler in the SAA7118 has
the following major blocks:
• Acquisition control (horizontal and vertical timer) and
task handling (the region/field/frame based processing)
• Prescaler, for horizontal down-scaling by an integer
factor, combined with appropriate band limiting filters,
especially anti-aliasing for CIF format
• Brightness, saturation, contrast control for scaled output
data
• Line buffer, with asynchronous read and write, to
support vertical up-scaling (e.g. for videophone
application, converting 240 into 288 lines, Y-C_B-C_R
4 : 2 : 2)
• Vertical scaling, with phase accurate Linear Phase
Interpolation (LPI) for zoom and downscale, or phase
accurate Accumulation Mode (ACM) for large
downscaling ratios and better alias suppression
• Variable Phase Delay (VPD), operates as horizontal
phase accurate interpolation for arbitrary non-integer
scaling ratios, supporting conversion between square
and rectangular pixel sampling
• Output formatter for scaled Y-C_B-C_R 4 : 2 : 2,
Y-C_B-C_R 4 : 1 : 1 and Y only (format also for raw data)
• FIFO, 32-bit wide, with 64 pixel capacity in Y-C_B-C_R
formats
• Output interface, 8 or 16-bit (only if extended by H-port)
data pins wide, synchronous or asynchronous
operation, with stream events on discrete pins, or coded
in the data stream.
The overall H and V zooming (HV_zoom) is restricted by
the input/output data rate relationships. With a safety
margin of 2% for running in and running out, the maximum
HV_zoom is equal to:
0.98 × _{i--n---_----p---i-x---e----l--×}-----i--n-T--_-_--l--ii-nn---pe----us---t-_×-_---f-o-i-e-u--l--td-_----^–_{c---y-T--c--_-l-e-v--_-_---pb---e-l-a-r--_-n---pk---ii-n-x---g-×}-----T----_---o---u----t-_---c---l--k-
For example:
1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit
data at 13.5 MHz data rate, 1 cycle per pixel; output:
8-bit data at 27 MHz, 2 cycles per pixel; the maximum
HV_zoom is equal to:
0.98 × _{7---2-2---00-----m×}-----s2---8-^–---8--2--_×-4----2-^×----_×-6---4-3---7--^µ---n-s---s- = 1.18
2. Input from X-port: 60 Hz, 720 pixel, 240 lines, 8-bit
data at 27 MHz data rate (ITU 656), 2 cycles per pixel;
output via I + H-port: 16-bit data at 27 MHz clock,
1 cycle per pixel; the maximum HV_zoom is equal to:
0.98 × ^{1---7-6---2.--6-0--6---}_×-6----2-m--4---s0----^–-_×----2-1--2---_×--^×---3--6-7--4---n---^µ-s--s-- = 2.34
The video scaler receives its input signal from the video
decoder or from the expansion port (X-port). It gets 16-bit
Y-C_B-C_R 4 : 2 : 2 input data at a continuous rate of
13.5 MHz from the decoder. Discontinuous data stream
can be accepted from the expansion port (X-port),
normally 8-bit wide ITU 656 like Y-C_B-C_R data,
accompanied by a pixel qualifier on XDQ.
The input data stream is sorted into two data paths, one for
luminance (or raw samples) and one for time multiplexed
chrominance C_B and C_R samples. An Y-C_B-C_R 4 : 1 : 1
input format is converted to 4 : 2 : 2 for the horizontal
prescaling and vertical filter scaling operation.
The scaler operation is defined by two programming pages
A and B, representing two different tasks, that can be
applied field alternating or to define two regions in a field
(e.g. with different scaling range, factors and signal source
during odd and even fields).
Each programming page contains control:
• For signal source selection and formats
• For task handling and trigger conditions
• For input and output acquisition window definition
• For H-prescaler, V-scaler and H-phase scaling.
Raw VBI-data is handled as specific input format and
needs its own programming page (equals own task).
2001 May 30
47