SAA7118 Datasheet, PDF (93/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
15 I²C-BUS DESCRIPTION
The SAA7118 supports the ‘fast mode’ I²C-bus specification extension (data rate up to 400 kbits/s).
15.1 I²C-bus format
S
SLAVE ADDRESS W
ACK-s
SUBADDRESS
ACK-s
a. Write procedure.
DATA
ACK-s P
data transferred
(n bytes + acknowledge)
MHB339
S
SLAVE ADDRESS W
ACK-s
Sr
SLAVE ADDRESS R
ACK-s
SUBADDRESS
DATA
ACK-s
ACK-m P
data transferred
(n bytes + acknowledge)
b. Read procedure (combined).
MHB340
Fig.50 I²C-bus format.
Table 35 Description of I²C-bus format
CODE
DESCRIPTION
S
START condition
Sr
repeated START condition
SLAVE ADDRESS W ‘0100 0010’ (42H, default) or ‘0100 0000’ (40H; note 1)
SLAVE ADDRESS R ‘0100 0011’ (43H, default) or ‘0100 0001’ (41H; note 1)
ACK-s
acknowledge generated by the slave
ACK-m
acknowledge generated by the master
SUBADDRESS
subaddress byte; see Tables 36 and 37
DATA
data byte; see Table 37; if more than one byte DATA is transmitted the subaddress pointer is
automatically incremented
P
STOP condition
X
read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver);
X = 1, order to read (the circuit is slave transmitter)
Note
1. If pin RTCO strapped to supply voltage via a 3.3 kΩ resistor.
2001 May 30
93