|
SAA7118 Datasheet, PDF (147/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input | |||
|
◁ |
Philips Semiconductors
Multistandard video decoder with adaptive
comb ï¬lter and component video input
Preliminary speciï¬cation
SAA7118
15.7.4 SUBADDRESS 8FH
Table 107 Status information scaler part; 8FH[7:0]; read only register
BIT
I2C-BUS
STATUS BIT
FUNCTION(1)
D7
XTRI
status on input pin XTRI, if not used for 3-state control, usable as hardware ï¬ag for software use
D6
ITRI
status on input pin ITRI, if not used for 3-state control, usable as hardware ï¬ag for software use
D5
FFIL
status of the internal âFIFO almost ï¬lledâ ï¬ag
D4 FFOV status of the internal âFIFO overï¬owâ ï¬ag
D3 PRDON copy of bit DPROG, can be used to detect power-up and start-up fails
D2 ERROF error ï¬ag of scalers output formatter, normally set, if the output processing needs to be
interrupted, due to input/output data rate conï¬icts, e.g. if output data rate is much too low and all
internal FIFO capacity used
D1 FIDSCI status of the ï¬eld sequence ID at the scalers input
D0 FIDSCO status of the ï¬eld sequence ID at the scalers output, scaler processing dependent
Note
1. Status information is unsynchronized and shows the actual status at the time of I2C-bus read.
15.7.5 SUBADDRESSES 90H AND C0H
Table 108 Task handling control; register set A [90H[7:6]] and B [C0H[7:6]]
X = donât care.
EVENT HANDLER CONTROL
Output ï¬eld ID is ï¬eld ID from scaler input
Output ï¬eld ID is task status ï¬ag, which changes every time an selected task
is activated (not synchronized to input ï¬eld ID)
Scaler SAV/EAV byte bit D7 and task ï¬ag = 1, default
Scaler SAV/EAV byte bit D7 and task ï¬ag = 0
CONTROL BITS D7 AND D6
CONLH
X
X
OFIDC
0
1
0
X
1
X
Table 109 Task handling control; register set A [90H[5:3]] and B [C0H[5:3]]
EVENT HANDLER CONTROL
Active task is carried out directly
1 ï¬eld is skipped before active task is carried out
... ï¬elds are skipped before active task is carried out
6 ï¬elds are skipped before active task is carried out
7 ï¬elds are skipped before active task is carried out
CONTROL BITS D5 TO D3
FSKP2
FSKP1
FSKP0
0
0
0
0
0
1
...
...
...
1
1
0
1
1
1
2001 May 30
147
|
▷ |