SAA7118 Datasheet, PDF (137/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
15.4.2 SUBADDRESS 2EH
Table 75 Interrupt mask 2; 2EH[6] and 2EH[1:0]
BIT
DESCRIPTION
D6 interrupt enable ‘horizontal PLL locked/unlocked’ (corresponding flag:
1EH[6])
D1 interrupt enable ‘colour standard changed 1’ (corresponding flag: 1EH[1])
D0 interrupt enable ‘colour standard changed 0’ (corresponding flag: 1EH[0])
SYMBOL VALUE FUNCTION
MHLCK
0 disabled
1 enabled
MDCSTD1 0 disabled
1 enabled
MDCSTD0 0 disabled
1 enabled
15.4.3 SUBADDRESS 2FH
Table 76 Interrupt mask 3; 2FH[7:5] and 2FH[3:0]
BIT
DESCRIPTION
SYMBOL VALUE FUNCTION
D7 interrupt enable ‘interlaced/non-interlaced source’ (corresponding flag:
1FH[7])
MINTL
0 disabled
1 enabled
D6 interrupt enable ‘horizontal and vertical lock reached/lost’ (corresponding
flag: 1FH[6])
MHLVLN
0 disabled
1 enabled
D5 interrupt enable ‘field frequency has changed’ (corresponding flag: 1FH[5]) MFIDT
0 disabled
1 enabled
D3 interrupt enable ‘colour stripe type 3 burst detected/lost’ (corresponding
flag: 1FH[3])
MTYPE3
0 disabled
1 enabled
D2 interrupt enable ‘colour stripe burst (any type) detected/lost’ (corresponding MCOLSTR 0 disabled
flag: 1FH[2])
1 enabled
D1 interrupt enable ‘copy protected signal found/lost’ (corresponding flag:
1FH[1])
MCOPRO
0 disabled
1 enabled
D0 interrupt enable ‘ready for capture/not ready’ (corresponding flag: 1FH[0]) MRDCAP 0 disabled
1 enabled
15.5 Programming register audio clock generation
See equations in Section 8.7 and examples in Tables 22 and 23.
15.5.1 SUBADDRESSES 30H TO 32H
Table 77 Audio master clock (AMCLK) cycles per field
SUBADDRESS
30H
31H
32H
ACPF7
ACPF15
−
ACPF6
ACPF14
−
CONTROL BITS D7 TO D0
ACPF5 ACPF4 ACPF3 ACPF2
ACPF13 ACPF12 ACPF11 ACPF10
−
−
−
−
ACPF1
ACPF9
ACPF17
ACPF0
ACPF8
ACPF16
2001 May 30
137