SAA7118 Datasheet, PDF(77/169 Page) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

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SAA7118 Datasheet, PDF (77/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

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Philips Semiconductors

Multistandard video decoder with adaptive

comb ï¬lter and component video input

Preliminary speciï¬cation

SAA7118

9.7 Host port for 16-bit extension of video data I/O (H-port)

The H-port pins HPD can be used for extension of the data I/O paths to 16-bit.

The I-port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H-port are enabled depending

on the I-port enable control. For I8_16 = 0, the HPD output is disabled.

Table 33 Signals dedicated to the host port

SYMBOL

PIN(1)

HPD7 to HPD0 G13, F14, F13, E14, E12,

E13, E11 and D14 (103,

105, 107 and 109 to 113)

I/O

DESCRIPTION

BIT

I/O 16-bit extension for digital I/O IPE[1:0] 87H[1:0], ITRI[8FH[6]]

(chrominance component) and I8_16[93H[6]]

Note

1. Pin numbers for QFP160 in parenthesis.

9.8 Basic input and output timing diagrams I-port

and X-port

9.8.1 I-PORT OUTPUT TIMING

The following diagrams illustrate the output timing via the

I-port. IGPH and IGPV are logic 1 active gate signals. If

reference pulses are programmed, these pulses are

generated on the rising edge of the logic 1 active gates.

Valid data is accompanied by the output data qualifier on

pin IDQ. In addition invalid cycles are marked with output

code 00H.

The IDQ output pin may be defined to be a gated clock

output signal (ICLK AND internal IDQ).

9.8.2 X-PORT INPUT TIMING

At the X-port the input timing requirements are the same

as those for the I-port output. But different to those below:

â¢ It is not necessary to mark invalid cycles with a 00H

code

â¢ No constraints on the input qualifier (can be a random

pattern)

â¢ XCLK may be a gated clock (XCLK AND external XDQ).

Remark: All timings illustrated in Figs 38 to 44 are given

for an uninterrupted output stream (no handshake with the

external hardware).

ICLK

IDQ

IPD[7:0] 00 FF 00

00 SAV 00 CB

IGPH

MHB550

Fig.38 Output timing I-port for serial 8-bit data at start of a line (ICODE = 1).

2001 May 30

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