SAA7118 Datasheet, PDF (87/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock input timing (XCLK)
T_cy
cycle time
δ
duty factors for
t_LLCH/t_LLC
t_r
rise time
t_f
fall time
31
−
45
ns
40
50
60
%
−
−
5
ns
−
−
5
ns
Data and control signal input timing X-port, related to XCLK input
t_SU;DAT
input data set-up
time
−
10
−
ns
t_HD;DAT
input data hold
time
−
3
−
ns
Clock output timing
C_L
output load
capacitance
15
−
50
pF
T_cy
cycle time
δ
duty factors for
t_XCLKH/t_XCLKL
t_r
rise time
0.6 to 2.6 V
t_f
fall time
2.6 to 0.6 V
35
−
39
ns
35
−
65
%
−
−
5
ns
−
−
5
ns
Data and control signal output timing X-port, related to XCLK output (for XPCK[1:0]83H[5:4] = 00 is default);
note 4
C_L
output load
capacitance
15
−
50
pF
t_OHD;DAT
output data hold C_L = 15 pF
time
−
14
−
ns
t_PD
propagation delay C_L = 15 pF
from positive edge
of XCLK output
−
24
−
ns
Control signal output timing RT port, related to LLC output
C_L
output load
capacitance
15
−
50
pF
t_OHD;DAT
t_PD
output hold time
propagation delay
from positive edge
of LLC output
C_L = 15 pF
C_L = 15 pF
−
14
−
ns
−
24
−
ns
2001 May 30
87