SAA7118 Datasheet, PDF (69/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
9 INPUT/OUTPUT INTERFACES AND PORTS
The SAA7118 has 5 different I/O interfaces:
• Analog video input interface, for analog CVBS and/or
Y and C input signals and/or component video signals
• Audio clock port
• Digital real-time signal port (RT port)
• Digital video expansion port (X-port), for unscaled digital
video input and output
• Digital image port (I-port) for scaled video data output
and programming
• Digital host port (H-port) for extension of the image port
or expansion port from 8 to 16-bit.
9.1 Analog terminals
The SAA7118 has 16 analog inputs AI41 to AI44,
AI31 to AI34, AI21 to AI24 and AI11 to AI14 for composite
video CVBS or S-video Y/C signal pairs or component
video input signals RGB plus separate sync (or Y-P_B-P_R
plus separate sync).
Component signals with e.g. sync-on-Y or sync-on-green
are also supported; they are fed to two ADC channels, one
for the video contents, the other for sync conversion.
Additionally, there are four differential reference inputs,
which must be connected to ground via a capacitor
equivalent to the decoupling capacitors at the 16 inputs.
There are no peripheral components required other than
these decoupling capacitors and 18 Ω/56 Ω termination
resistors, one set per connected input signal (see also
application example in Fig.47). Four anti-alias filters are
integrated.
Clamp and gain control for the four ADCs are also
integrated. An analog video output (pin AOUT) is provided
for testing purposes.
Table 24 Analog pin description
SYMBOL
PIN⁽¹⁾
I/O
DESCRIPTION
BIT
AI11 to AI14
J2, K1, K2 and L3
(27, 29, 31 and 34)
AI21 to AI24
G4, G3, H2 and J3
(19, 21, 23 and 26)
AI31 to AI34
E3, F2, F3 and G1
(11, 13, 15 and 18)
AI41 to AI44
B1, D2, D1 and E1
(2, 5, 7 and 10)
AOUT
M1 (36)
AI1D, AI2D, K3, H1, F1 and D3
AI3D and AI4D (30, 22, 14 and 6)
I analog video signal inputs, e.g. 16 CVBS signals or
eight Y/C pairs, or four RGB plus separate sync (or
Y-P_B-P_R plus separate sync) signal groups can be
connected simultaneously to this device; many
combinations are possible; see Figs 51 to 91
O analog video output, for test purposes
I analog reference pins for differential ADC operation;
connect to ground via 47 nF
MODE5 to MODE0
AOSL2 to AOSL0
−
Note
1. Pin numbers for QFP160 in parenthesis.
2001 May 30
69