F81866A Datasheet, PDF (97/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

G3 stage)
S5 S0
S5
S0
S5
VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
F81866A
Keep last
state
ATXPG_IN, VCC (PWOK), VSB (RSMRST) and S3 signals to detect the sleep state while AC
loss occur. One of the signal (ATXPG_IN or VCC under 2.8V or VSB under 2.8V) sinks low,
SIO will latch the S3 signal to decide the system to be at “always on” or “always off” mode.
See below table:
Signal
AC loss state
ATXPG
VSB
VCC
AC resume
AC loss in S0/S1 (S3=1)
Always on
AC loss in S3/S4/S5 (S3=0)
Always off
6.8.2Intel Power Saving Function Deep Sleep Well (DSW)
The F81866A supports Intel Cougar Point (CPT) Chipset timing for Sandy Bridge (Sugar Bay or Huron
River Platform). There are 4 pins for CPT control: SUS_WARN#, SUS_ACK#, SLP_SUS# and DPWROK.
For entering the Intel Deep Sleep Well (DSW) state, the PCH will assert SUS_WARN# (low level) and
turn off 5VDUAL. After the level of 5VDUAL is lower than 1.05V, F81866A will assert SUS_ACK# to inform
PCH it is ready for entering DSW. Finally, PCH will ramp down the internal VccSUS and assert SLP_SUS# to
F81866A. F81866A will turn off the 5VSB and 3VSB by ERP_CTRL0# and enter the DSW state.
To exit DSW state, PCH will de-assert SLP_SUS#, turn on the SUS rail FETs and ramp up internal
1.05V VccSUS. After the SUS rails voltages are up, RSMRST# will be desserted and the PCH will release
SUS_WARN# so that the 5VDUAL will ramp up.
Because the DSW function is controlled by the F81866A instead of controlled by the PCH directly, there
will be more wakeup events such as LAN, KB/Mouse, GPIO0x, GPIO1x, SIO RI# wake up rather than the 3
wakeup events (RTC, Power Button and GPIO27) for Intel DSW.
97
Jan, 2012
V0. 12P