F81866A Datasheet, PDF (46/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
Case Open, Alert, OVT Mode Register ⎯ Index 02h
Bit
Name
R/W Reset Default
7
Reserved
R/W
-
0 ^{Dummy register.}
Description
6 CASE_BEEP_EN R/W 5VSB
5-4
OVT_MODE R/W 5VSB
3
Reserved
R/W
-
0: Disable case open event output via BEEP.
0
1: Enable case open event output via BEEP.
00: The OVT# will be low active level mode.
0 ^{01: The OVT# will be low pulse mode.}
10: The OVT# will indicate by 1Hz LED function.
11: The OVT# will indicate by (400/800HZ) BEEP output.
0 ^{Dummy register.}
0: Disable case open event output via PME.
2
CASE_SMI_EN
R/W 5VSB 0
1: Enable case open event output via PME.
00: The ALERT# will be low active level mode.
1-0
ALERT_MODE R/W 5VSB
0 ^{01: The ALERT# will be high active level mode.}
10: The ALERT# will indicate by 1Hz LED function.
11: The ALERT# will indicate by (400/800HZ) BEEP output.
Case Open Status Register ⎯ Index 03h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
R/W
-
0 ^Reserved
Case open event status write 1 to clear if case open event cleared. (This
0
CASE_STS
R/W VBAT
0 _{bit is powered by VBAT.)}
6.4.2.2PECI/TSI/I2C Setting
TSI Or IBEX Control Register ⎯ Index 08h
Bit
Name
R/W Reset Default
Description
7-1
TSI_ADDR
R/W 5VSB 26h AMD TSI or Intel IBEX slave address.
0
Reserved
-
-
- Reserved
I2C Address Control Register ⎯ Index 09h
Bit
Name
R/W Reset Default
Description
I2C__ADDR[7:1] is the slave address sent by the embedded master
7-1
I2C _ADDR
R/W 5VSB
0
when using a block write command
0
Reserved
R/W
-
0 Reserved
46
Jan, 2012
V0. 12P