F81866A Datasheet, PDF (193/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

70
IRQ Channel Select Register
F0
IRQ Share Register
F1
IR Mode Register
F2
Clock Select Register
F4
9bit-mode Slave Address Register
F5
9bit-mode Slave Address Mask Register
F0
IRQ Share Register
F6
FIFO Mode Register
F81866A
- - - - 0011
00000000
- - - 00100
- - - 00000
- - - - - - 00
00000000
00000000
00000 - 00
7.15.1UART 6 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
- Reserved
0: disable UART 6 I/O Port.
0
UART6_EN
R/W LRESET# 0
1: enable UART 6 I/O Port.
Description
7.15.2Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W LRESET# 00h The MSB of UART 6 base address.
7.15.3Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W LRESET# 00h The LSB of UART 6 base address.
7.15.4IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0 SELUART6IRQ R/W LRESET# 3h Select the IRQ channel for UART 6.
7.15.5IRQ Share Register ⎯ Index F0h
Bit
Name
R/W Reset Default
Description
0: normal UART function
7
9BIT_MODE
R/W LRESET# 0 ^{1: enable 9-bit mode (multi-drop mode).}
In the 9-bit mode, the parity bit becomes the address/data bit.
This bit works only in 9-bit mode.
0: the SM2 bit will be cleared by host, so that data could be received.
6
AUTO_ADDR
R/W LRESET# 0 _{1: the SM2 bit will be cleared by hardware according to the sent address and}
the given address (or broadcast address derived by SADDR and SADEN)
5
RS485_INV
R/W LRESET# 0 Invert RTS# if RS485_EN is set.
0: RS232 driver.
4
RS485_EN
R/W LRESET# 0 1: RS485 driver. RTS# is driven high automatically when transmitting
data, otherwise is kept low.
0 : No reception delay when SIR is changed from TX to RX.
3
RXW4C_IR
R/W LRESET# 0 _{1 : Reception delay 4 character-time when SIR is changed from TX to RX.}
193
Jan, 2012
V0. 12P