F81866A Datasheet, PDF (8/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
6.6.2.7 GPIO6x ................................................................................................................... 92
6.6.2.8 GPIO7x ................................................................................................................... 93
6.6.2.9 GPIO8x ................................................................................................................... 93
6.7
Watchdog Timer Function ....................................................................................... 93
6.8
ACPI Function ......................................................................................................... 94
6.8.1
Power Control............................................................................................................. 95
6.8.1.1 Wake Up Via Sleep State ........................................................................................ 95
6.8.1.2 Wake Up Stage Detection ....................................................................................... 95
6.8.1.3 AC Loss & Resume Control Methods ..................................................................... 96
6.8.2
Intel Power Saving Function Deep Sleep Well (DSW) ............................................... 97
6.8.3
Power Saving Controller (Fintek ERP Mode) ............................................................. 99
6.8.4
ACPI Timing ............................................................................................................. 103
6.8.4.1 G3 To S0 ............................................................................................................... 103
6.8.4.2 G3 To S0 (only DSW) ............................................................................................ 104
6.8.4.3 G3 To S0 (DSW & ERP, AC Resume Green Bold Line) ........................................ 105
6.8.4.4 DSW To S0............................................................................................................ 106
6.8.4.5 S0 to DSW ............................................................................................................ 107
6.8.4.6 S0 to G3’ ............................................................................................................... 108
6.8.5
PWOK Signals.......................................................................................................... 109
6.9 UART…………. .................................................................................................................... 109
6.9.1
UART Device Register .......................................................................................... 109
6.9.2
Programmable Baud Rate..................................................................................... 113
6.10 AMD TSI and Intel PECI 3.0 Functions ................................................................................ 114
6.11 Over Voltage Protection ....................................................................................................... 115
7. Register Description ................................................................................................... 116
7.1 Global Control Registers ...................................................................................................... 116
7.2 Multifunction Function Register Mapping Table ................................................................... 124
7.2.1
Multi Function Register Mapping For FDC ............................................................... 124
7.2.2
Multi Function Register Mapping For Parallel Port (LPT) ......................................... 125
7.2.3
Multi Function Register Mapping For Hardware Monitor .......................................... 125
7.2.4
Multi Function Register Mapping For KBC (PS/2 Mouse) ........................................ 126
7.2.5
Multi Function Register Mapping For GPIO0x.......................................................... 126
7.2.6
Multi Function Register Mapping For GPIO1x.......................................................... 126
7.2.7
Multi Function Register Mapping For GPIO2x.......................................................... 127
7.2.8
Multi Function Register Mapping For GPIO3x.......................................................... 127
7.2.9
Multi Function Register Mapping For GPIO4x.......................................................... 128
7.2.10
Multi Function Register Mapping For GPIO5x.......................................................... 128
Jan, 2012
V0.12P