F81866A Datasheet, PDF (165/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

7.7.12.4GPIO8 Drive Enable Register ⎯ Index 8Bh
Bit
Name
R/W Reset Default
Description
0: GPIO87 is open drain in output mode.
7 GPIO87_DRV_EN R/W LRESET# 0
1: GPIO87 is push pull in output mode.
0: GPIO86 is open drain in output mode.
6 GPIO86_DRV_EN R/W LRESET# 0
1: GPIO86 is push pull in output mode.
0: GPIO85 is open drain in output mode.
5 GPIO85_DRV_EN R/W LRESET# 0
1: GPIO85 is push pull in output mode.
0: GPIO84 is open drain in output mode.
4 GPIO84_DRV_EN R/W LRESET# 0
1: GPIO84 is push pull in output mode.
0: GPIO83 is open drain in output mode.
3 GPIO83_DRV_EN R/W LRESET# 0
1: GPIO83 is push pull in output mode.
0: GPIO82 is open drain in output mode.
2 GPIO82_DRV_EN R/W LRESET# 0
1: GPIO82 is push pull in output mode.
0: GPIO81 is open drain in output mode.
1 GPIO81_DRV_EN R/W LRESET# 0
1: GPIO81 is push pull in output mode.
0: GPIO80 is open drain in output mode.
0 GPIO80_DRV_EN R/W LRESET# 0
1: GPIO80 is push pull in output mode.
F81866A
7.7.12.5GPIO8 SMI Enable Register ⎯ Index 8Eh
Bit
Name
R/W Reset Default
Description
0: Disable SMI event.
7 GPIO87_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO87_SMI_ST is set.
0: Disable SMI event.
6 GPIO86_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO86_SMI_ST is set.
0: Disable SMI event.
5 GPIO85_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO85_SMI_ST is set.
0: Disable SMI event.
4 GPIO84_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO84_SMI_ST is set.
0: Disable SMI event.
3 GPIO83_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO83_SMI_ST is set.
0: Disable SMI event.
2 GPIO82_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO82_SMI_ST is set.
0: Disable SMI event.
1 GPIO81_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO81_SMI_ST is set.
0: Disable SMI event.
0 GPIO80_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO80_SMI_ST is set.
7.7.12.6GPIO8 SMI Status Register ⎯ Index 8Fh
Bit
Name
R/W Reset Default
Description
0: No SMI event.
7 GPIO87_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO87 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
165
Jan, 2012
V0. 12P