F81866A Datasheet, PDF (202/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

12.Application Circuit
F81866A
PS_ON#
PWROK
RSMRST#
VBAT
COPEN#
DPWROK
S5#
PWROK
RSMRST#
D-
D2+
D1+
VREF
VIN4
VIN3
VIN2
VIN1
R1
0
U1
VSB3V
FANIN1
FANCTL1
FANIN2
FANCTL2
SLCT
PE
BUSY
ACK#
SLIN#
INIT#
ERR#
AFD#
STB#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VCC3V
DCD1#
RI1#
CTS1#
DTR1#
RTS1#
DSR1#
SOUT1
SIN1
DTR1#
RTS1#
SOUT1
97
98
99
100
3VSB
FANIN1
FANCTL1/PWM_DC1
101
102
103
104
FANIN2
FANCTL2/PWM_DC2
FANIN3/SLCT
GPIO70/PE/FANCTL3/PWM_DC3
105 ^GPIO71/BUSY
106
107
108
109
GPIO72/ACK#
GPIO73/SLIN#
GPIO74/INIT#
GPIO75/ERR#
110
111
112
113
GPIO76/AFD#
GPIO77/STB#
GPIO80/PD0
GPIO81/PD1
114
115
116
117
GPIO82/PD2
GPIO83/PD3
GPIO84/PD4
GPIO85/PD5
118
119
120
121
GPIO86/PD6
GPIO87/PD7
3VCC
DCD1#
122
123
124
125
126
RI1#
CTS1#
DTR1#/FAN_40_100
RTS1#/Conf ig4E_2E
DSR1#
127
128
SOUT1/I2C_ADDR
SIN1
GND
F81866AD
F81866
DCD2#
RI2#
CTS2#
DTR2#
RTS2#
DSR2#
SOUT2
SIN2
DENSEL#/RTS6#
MOA#/SIN6
DRVA#/SOUT6
WDATA#/DCD6#
DIR#/RI6#
STEP#/CTS6#
HDSEL#/DTR6#
WGATE#/DSR6#
DENSEL#
MOA#
DRVA#
WDATA#
DIR#
STEP#
HDSEL#
WGATE#
S3#
PWSOUT#
ATXPG_IN
PWSIN#
ATXPG_IN
ALERT#
OVT#
PME#
R106 10
5VA
PECI
BEEP
GPIO14
WDTRST#
GPIO14
IRRX
IRTX
LED_VCC
LED_VSB
C56
0.1U
KCLK
KDATA
MCLK/SDA
MDATA/SCL
64
63
62
61
60
I_VSB3V
GPIO07/RTS5#
GPIO06/SIN5
GPIO05/SOUT5
59
58
57
56
SLP_SUS#/GPIO04 ₅₅
SUS_ACK#/GPIO03
SUS_WARN#/GPIO02
ERP_CTRL1#/GPIO01
ERP_CTRL0#/GPIO00
54
53
52
51
SIN4/GPIO47
SOUT4/GPIO46
DSR4#/GPIO45
RTS4#/GPIO44
50
49
48
47
DTR4#/GPIO43
CTS4#/GPIO42
RI4#/GPIO41
DCD4#/GPIO40
46
45
44
43
SIN3/GPIO37
SOUT3/GPIO36
DSR3#/GPIO35
RTS3#/GPIO34
42
41
40
39
DTR3#/GPIO33
CTS3#/GPIO32
RI3#/GPIO31
DCD3#/GPIO30
GA20
38
37
36
35
34
KBRST#
CLKIN
33
C1
0.1U
KCLK
KDATA
MCLK
MDRA7TA
3VA
0_X
D1 DIODE
RTS5#
SIN5
SOUT5
SLP_SUS#
SUS_ACK#
SUS_WARN#
ERP_CTRL1#
ERP_CTRL0#
SIN4
SOUT4
DSR4#
RTS4#
DTR4#
CTS4#
RI4#
DCD4#
SIN3
SOUT3
DSR3#
RTS3#
DTR3#
CTS3#
RI3#
DCD3#
GA20
KBRST#
CLKIN
ATXPG_IN
C81 Decouple ATX
0.1U ^{power supply}
noise.
VCC5V
WPT#
R2 1K INDEX#
R3 1K TRK0#
R4 1K RDATA#
R5 1K DSKCHG#
R6 1K
J1
1
3
5
7
9
11
1
3
5
7
9
13
15
17
19
11
13
15
17
21
23
25
27
29
19
21
23
25
27
31
33
29
31
33
2
2
4
6
8
10
4
6
8
10
12
12
14
16
18
14
16
18
20
20
22
24
26
28
22
24
26
28
30
30
32
34
32
34
HEADER 17X2
FLOPPY
DENSEL#
INDEX#
MOA#
DRVA#
DIR#
STEP#
WDATA#
WGATE#
TRK0#
WPT#
RDATA#
HDSEL#
DSKCHG#
VSB3V VCC3V
R8 R9
4.7K 4.7K
RSMRST#
PWROK
RSMRST# AND PWROK PULL UP
SOUT1
RTS1#
DTR1#
GPIO14
DTR2#
R10 R11 R12 R13 R14
560 560 560 560 560
POWER TRIP R
R10 OFF: ALARM mode
R11 OFF: ATX MODE
R12 OFF: FAN 40%
R13 OFF: CONFIG 4E
R14 OFF: 0x5C
ON: FORCE mode
ON: AT MODE
ON: FAN 100%
ON: CONFIG 2E
ON: 0x5A
DSKCHG#
WPT#
INDEX#
TRK0#
RDATA#
PCICLK
VCC3V
LAD3
LAD2
LAD1
LAD0
LFRAME#
SERIRQ
LDRQ#
LRESET#
DSKCHG#/DSR5#
WPT#/DTR5#
INDEX#/CTS5#
TRK0#/RI5#
RDATA#/DCD5#
202
VBAT D2 DIODEVBAT
D3 DIODEVSB3V
VCC3V VCC3V VSB3V VSB5V VBAT
C2
0.1U
C3
0.1U
C4
0.1U
C5
0.1U
C6
0.1U
(PLACE THE CAPCITOR CLOSE TO IC)
Title
Feature Integration Technology Inc.
Size Document Number
CustomF81866AD
Date:
Tuesday , Nov ember 08, 2011 Sheet
Rev
<Rev Code>
1
of 8
Jan, 2012
V0. 12P