F81866A Datasheet, PDF (51/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
Block Write Count Register – Index ECh
Bit
Name
R/W Reset Default
Description
This bit is used to select the register in index E0h to E9h.
7
MCH_BANK_SEL R/W 5VSB
0
Set “0” to read the temperature bank and “1” to access the data bank.
6
Reserved
-
-
0 Reserved
5-0 BLOCK_WR_CNT R/W 5VSB
Use the register to specify the byte count of block write protocol. Support
0
up to 10 bytes.
I2C Command Byte/TSI Command Byte – Index EDh
Bit
Name
R/W Reset Default
Description
There are actual two bytes for this index. TSI_CMD_PROG select which
byte to be programmed:
7-0 I2C_CMD/TSI_CMD R/W 5VSB
0: I2C_CMD, which is the command code for write byte/word, read
0/1
byte/word, block write/read and process call protocol.
1: TSI_CMD, which is the command code for Intel temperature interface
block read protocol and the data byte for AMD TSI send byte protocol.
I2C Status – Index EEh
Bit
Name
R/W Reset Default
Description
Set 1 to pending auto TSI accessing. (In AMD model, auto accessing will
issue a send-byte followed a receive-byte; In Intel model, auto accessing
7
TSI_PENDING
R/W LRESET#
0
will issue a block read).
To use the SCL/ SDA as I2C master, set this bit to “1” first.
6
TSI_CMD_PROG R/W 5VSB
0 Set 1 to program TSI_CMD.
Kill the current I2C transfer and return the state machine to idle. It will set
5
PROC_KILL
R/W 5VSB
0
a fail status if the current transfer is not completed.
This is set when PROC_KI LL kill an un-completed transfer. It will be
4
FAIL_STS
R 5VSB
0
auto cleared by next I2C transfer.
This is the arbitration lost status if I2C command is issued. Auto cleared
3
I2C_ABT_ERR
R 5VSB
0
by next I2C command.
This is the timeout status if I2C command is issued. Auto cleared by next
2
I2C_TO_ERR
R 5VSB
0
I2C command.
This is the NACK error status if I2C command is issued. Auto cleared by
1
I2C_NAC_ERR
R 5VSB
0
next I2C command.
0: I2C transfer is in process.
0
I2C_ READY
R 5VSB
1
1: Ready for next I2C command.
51
Jan, 2012
V0. 12P