F81866A Datasheet, PDF (141/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
7.7.3.2GPIO IRQ Sharing Mode Register 　 Index 7Fh
Bit
Name
R/W _Reset Default
Description
GPIO8 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
7-6 GP8_IRQ_MODE R/W _LRESET# 0 10 : Sharing IRQ active high Level.
11 : Reserved.
This bit is effective when IRQ is sharing with other device
(GP8_IRQ_SHARE is “1”).
GPIO5 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
5-4 GP5_IRQ_MODE R/W LRESET# 0 10 : Sharing IRQ active high Level.
11 : Reserved.
This bit is effective when IRQ is sharing with other device
(GP5_IRQ_SHARE is “1”).
GPIO1 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
3-2 GP1_IRQ_MODE R/W LRESET# 0 10 : Sharing IRQ active high Level.
11 : Reserved.
This bit is effective when IRQ is sharing with other device
(GP1_IRQ_SHARE is “1”).
GPIO0 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
1-0 GP0_IRQ_MODE R/W LRESET# 0 10 : Sharing IRQ active high Level.
11 : Reserved.
This bit is effective when IRQ is sharing with other device
(GP0_IRQ_SHARE is “1”).
7.7.4.GPIO0x Configuration Registers
Register
0x[HEX]
F0
F1
Register Name
GPIO0 Output Enable Register
GPIO0 Output Data Register
MSB
Default Value
LSB
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
141
Jan, 2012
V0. 12P