F81866A Datasheet, PDF (135/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

7.4.1Parallel Port Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
- Reserved
0: disable Parallel Port.
0
PRT_EN
R/W LRESET# 1
1: enable Parallel Port.
Description
7.4.2Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W LRESET# 03h The MSB of Parallel Port base address.
7.4.3Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W LRESET# 78h The LSB of Parallel Port base address.
7.4.4IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0
SELPRTIRQ
R/W LRESET# 7h Select the IRQ channel for Parallel Port.
7.4.5DMA Channel Select Register ⎯ Index 74h
Bit
Name
R/W Reset Default
Description
7-5
Reserved
-
-
- Reserved.
0: non-burst mode DMA.
4 ECP_DMA_MODE R/W LRESET# 0
1: enable burst mode DMA.
3
Reserved
-
-
- Reserved.
2-0
SELPRTDMA R/W LRESET# 011 Select the DMA channel for Parallel Port.
F81866A
7.4.6PRT Mode Select Register ⎯ Index F0h
Bit
Name
R/W Reset Default
Description
Interrupt mode in non-ECP mode.
7 SPP_IRQ_MODE R/W LRESET# 0 _{0: Level mode.}
1: Pulse mode.
6-3 ECP_FIFO_THR R/W LRESET# 1000 ECP FIFO threshold.
135
Jan, 2012
V0. 12P