F81866A Datasheet, PDF (18/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

5.2 Clock
Pin
Pin Name
32
PCICLK
33
CLKIN
F81866A
Type
IN_st
IN_st
PWR
3VCC
3VCC
Description
33MHz PCI clock input.
System clock input. According to the input frequency
14.318/24/48MHz (default 48MHz).
5.3 LPC Interface
Pin
Pin Name
Type
23
LRESET#
24
LDRQ#
25
SERIRQ
26
LFRAME#
IN_st
O₁₆
I/O_16st
IN_st
27-30
32
LAD[0:3]
PCICLK
I/O_16st
IN_st
PWR
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
Description
Reset signal. It can connect to PCIRST# signal on the
host.
Encoded DMA Request signal.
Serial IRQ input/Output.
Indicates start of a new cycle or termination of a broken
cycle.
These signal lines communicate address, control, and
data information over the LPC bus between a host and
a peripheral.
33MHz PCI clock input.
5.4 FDC, & GPIO
Pin
Pin Name
Type
GPIO50
I/OOD_{14st, 5v}
DENSEL#
OD_14,5v
9
RTS6#
O₁₄
GPIO51
I/OOD_{14st, 5v}
10
MOA#
OD_14,5v
SIN6
IN_st,5v
GPIO52
I/OOD_{14st, 5v}
11
DRVA#
OD_14,5v
SOUT6
GPIO53
O₁₄
I/OOD_{14st, 5v}
12
WDATA#
OD_14,5v
DCD6#
IN_st,5v
PWR
3VCC
3VCC
3VCC
3VCC
Description
General Purpose IO.
Drive Density Select.
Set to 1 – High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
UART Request To Send. An active low signal
informs the modem or data set that the controller is
ready to send data.
General Purpose IO.
Motor A On. When set to 0, this pin enables disk
drive 0. This is an open drain output.
UART Serial Input. Used to receive serial data
through the communication link.
General Purpose IO.
Drive Select A. When set to 0, this pin enables disk
drive A. This is an open drain output.
UART Serial Output. Used to transmit serial data
out to the communication link.
General Purpose IO.
Write data. This logic low open drain writes
pre-compensation serial data to the selected FDD.
An open drain output.
Data Carrier Detect. An active low signal indicates
18
Jan, 2012
V0. 12P