F81866A Datasheet, PDF (63/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
Voltage-Protect Configuration Register ⎯ Index 12h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
PSON# de-active time select in alarm mode of voltage protection.
00: PSON# tri-state 0.5 sec and then inverted of S3# when over voltage or
under voltage occurred.
01: PSON# tri-state 1 sec and then inverted of S3# when over voltage or
3-2
PU_TIME
R/W VBAT 2’h1 under voltage occurred.
10: PSON# tri-state 2 sec and then inverted of S3# when over voltage or
under voltage occurred.
11: PSON# tri-state 4 sec and then inverted of S3# when over voltage or
under voltage occurred.
VP_EN_DELAY could set the delay time to start voltage protecting after
VDD power is ok when OVP_MODE is 1. (OVP_MODE is strapped by
RTS1# pin)
1-0 VP_EN_DELAY R/W VBAT 2’h2 00: bypass
01: 50ms
10: 100ms
11: 200ms
Voltage1 PME# Enable Register ⎯ Index 14h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
0 ^Reserved
1
EN_V1_PME
R/W 5VSB
A one enables the corresponding interrupt status bit for PME# interrupt.
0 _{Set this bit 1 to enable PME# function for VIN1.}
0
Reserved
-
-
- ^Reserved
Voltage1 Interrupt Status Register ⎯ Index 15h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
--
-
0 ^Reserved
1
V1_ EXC _STS R/W 5VSB
0 ^{This bit is set when the VIN1 is over the high limit. Write 1 to clear this bit,}
write 0 will be ignored.
0
Reserved
-
-
- ^Reserved
Voltage1 Exceeds Real Time Status Register 1 ⎯ Index 16h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
--
-
0 Reserved
1
V1_EXC
RO 5VSB
A one indicates VIN1 exceeds the high limit. A zero indicates VIN1 is in the
0 _{safe region.}
0
Reserved
--
-
0 Reserved
63
Jan, 2012
V0. 12P