F81866A Datasheet, PDF (174/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

6 _{LED_VSB_S5_MODE_ADD R/W} ^VBAT
5 _{LED_VSB_S3_MODE_ADD R/W} ^VBAT
4 _{LED_VSB_S0_MODE_ADD R/W} ^VBAT
3
Reserved
-
-
2 _{LED_VCC_S5_MODE_ADD R/W} ^VBAT
1 _{LED_VCC_S3_MODE_ADD R/W} ^VBAT
0 _{LED_VCC_S0_MODE_ADD R/W} ^VBAT
0 ^{Refer to LED_VSB_S5_MODE.}
0 ^{Refer to LED_VSB_S3_MODE.}
0 ^{Refer to LED_VSB_S0_MODE.}
- Reserved
0 ^{Refer to LED_VCC_S5_MODE.}
0 ^{Refer to LED_VCC_S3_MODE.}
0 ^{Refer to LED_VCC_S0_MODE.}
F81866A
7.9.11LED Control Register 3 ⎯ Index FAh
Bit
Name
R/W _Reset Default
Description
7
Reserved
-
-
- Reserved
6
LED_VSB_DS3 R/W VBAT
5-4 _{LED_VSB_S5_MODE R/W VBAT}
3-2 _{LED_VSB_S3_MODE R/W VBAT}
1-0 _{LED_VSB_S0_MODE R/W VBAT}
0: Disable LED_VSB deep S3 mode.
0
1: Enable LED_VSB deep S3 mode. Output 0.25HZ clock with 25% duty.
The three bits {LED_VSB_S5_MODE_ADD, LED_VSB_S5_MODE [1:0]}
select the LED_VSB mode in S5 state.
000: Sink low.
001: Tri-state or drive high control by GPIO10_DRV_EN.
010: 0.5Hz clock with 50% duty.
00 _{011: 1Hz clock with 50% duty.}
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
The three bits {LED_VSB_S3_MODE_ADD, LED_VSB_S3_MODE [1:0]}
select the LED_VSB mode in S3 state.
000: Sink low.
001: Tri-state or drive high control by GPIO10_DRV_EN.
010: 0.5Hz clock with 50% duty.
00 _{011: 1Hz clock with 50% duty.}
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
The three bits {LED_VSB_S0_MODE_ADD, LED_VSB_S0_MODE [1:0]}
select the LED_VSB mode in S0 state.
000: Sink low.
001: Tri-state or drive high control by GPIO10_DRV_EN.
010: 0.5Hz clock with 50% duty.
00
011: 1Hz clock with 50% duty.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
174
Jan, 2012
V0. 12P