F81866A Datasheet, PDF (139/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
7.7.1.3Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
The LSB of KBC data port address. When GPIO_DEC_RANGE is “0”, only 8
bytes are decoded:
Base + 0: index port.
Base + 1: data port.
Base + 2: GPIO8 data register.
Base + 3: GPIO7 data register.
Base + 4: GPIO6 data register.
Base + 5: GPIO5 data register.
Base + 6: GPIO0 data register.
Base + 7: GPIO1 data register.
If GPIO_DEC_RANGE is set to “1”, more 8 bytes are decoded:
7-0 BASE_ADDR_LO R/W LRESET# 00h _{Base + 8: GPIO2 data register.}
Base + 9: GPIO3 data register.
Base + 10: GPIO4 data register.
Otherwise: Reserved.
There are three ways to access the GPIO registers.
1. Use configuration register port 0x4E/0x4F (or 0x2E/0x2F), the LDN for
GPIO is 0x06.
2. Use GPIO index/data port. Write index to index port first and then
read/write the register.
3. Use digital I/O port. The way only access GPIO data register. Write data to
this port will control the data output register. And read this port will read the
pin status register.
7.7.2.GPIO IRQ Channel Select Configuration Registers
Register
0x[HEX]
70
71
72
73
Register Name
GPIO0 IRQ Channel Select Register
GPIO1 IRQ Channel Select Register
GPIO5 IRQ Channel Select Register
GPIO8 IRQ Channel Select Register
MSB
-
-
-
-
-
-
-
-
Default Value
LSB
-
-
0
0
0
1
-
-
0
0
0
1
-
-
0
0
0
1
-
-
0
0
0
1
7.7.2.1GPIO0 IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0
SELGP0IRQ
R/W LRESET# 1h Select the IRQ channel for GPIO0 interrupt.
7.7.2.2GPIO1 IRQ Channel Select Register ⎯ Index 71h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0
SELGP1IRQ
R/W LRESET# 1h Select the IRQ channel for GPIO1 interrupt.
139
Jan, 2012
V0. 12P