F81866A Datasheet, PDF (142/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F2
GPIO0 Pin Status Register
F3
GPIO0 Drive Enable Register
F4
GPIO0 Output Mode 1 Register
F5
GPIO0 Output Mode 2 Register
F6
GPIO0 Pulse Width Select 1 Register
F7
GPIO0 Pulse Width Select 2 Register
F8
GPIO0 SMI Enable Register
F9
GPIO0 SMI Status Register
F81866A
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7.7.4.1GPIO0 Output Enable Register ⎯ Index F0h
Bit
Name
R/W Reset Default
0: GPIO07 is input.
7
GPIO07_OE R/W 5VSB
0
1: GPIO07 is output.
0: GPIO06 is input.
6
GPIO06_OE R/W 5VSB
0
1: GPIO06 is output.
0: GPIO05 is input.
5
GPIO05_OE R/W 5VSB
0
1: GPIO05 is output.
0: GPIO04 is input.
4
GPIO04_OE R/W 5VSB
0
1: GPIO04 is output.
0: GPIO03 is input.
3
GPIO03_OE R/W 5VSB
0
1: GPIO03 is output.
0: GPIO02 is input.
2
GPIO02_OE R/W 5VSB
0
1: GPIO02 is output.
0: GPIO01 is input.
1
GPIO01_OE R/W 5VSB
0
1: GPIO01 is output.
0: GPIO00 is input.
0
GPIO00_OE R/W 5VSB
0
1: GPIO00 is output.
Description
7.7.4.2GPIO0 Output Data Register ⎯ Index F1h (This byte could be also written by base address + 6)
Bit
Name
R/W Reset Default
Description
GPIO07 supports pulse mode.
When pulse mode is selected, write “1” to this bit will assert a pulse from
GPIO07. Auto clear when pulse is finished.
7
GPIO07_VAL R/W 5VSB 0 When level mode is selected, write 0/1 to this bit will set the level of GPIO07.
0: outputs 0 when in output mode.
1: outputs 1 when in output mode. GPIO07 will be tri-state if GPIO07_DRV is
clear to “0”.
142
Jan, 2012
V0. 12P