F81866A Datasheet, PDF (77/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

FAN1_
4 INTERPOLATION_E R/W 5VSB
N
FAN1_JUMP
3
R/W 5VSB
_HIGH_EN
FAN1_JUMP
2
R/W 5VSB
_LOW_EN
1-0 FAN1_TEMP_SEL R/W 5VSB
F81866A
1 Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN1 duty movement when temperature over
highest boundary.
0: The FAN1 duty will increases with the slope selected by
1 FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC1SPEED1
register.
This bit only activates in duty mode.
This register controls the FAN1 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN1 duty will decreases with the slope selected by
1 FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC2SPEED1
register.
This bit only activates in duty mode.
This registers company with FAN1_TEMP_SEL_DIG select the
temperature source for controlling FAN1. The following value is
comprised by {FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL}
000: fan1 follows PECI temperature (CR7Eh)
001: fan1 follows temperature 1 (CR72h).
010: fan1 follows temperature 2 (CR74h).
01
011: fan1 follows temperature 0 (CR70h).
100: fan1 follows IBX/TSI CPU temperature (CR7Ah)
101: fan1 follows IBX PCH temperature (CR7Bh).
110: fan1 follows IBX MCH temperature (CR7Ch).
111: fan1 follows IBX maximum temperature (CR7Dh).
Others are reserved.
B. FAN2 Index B0h~BFh
Address
Attribute
Reset
B0h
RO
3VCC
B1h
RO
3VCC
Default Value
Description
FAN2 count reading (MSB). At the moment of reading this
8’h0f
register, the LSB will be latched. This will prevent from data
updating when reading. To read the fan count correctly, read
MSB first and followed read the LSB.
8’hff
FAN2 count reading (LSB).
77
Jan, 2012
V0. 12P