F81866A Datasheet, PDF (132/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
7.2.22Multi Function Register Mapping For UART 6
PIN No.
PIN FULL NAME
PIN SELECT
PIN9
GPIO50/DENSEL#/RTS6#
RTS6#
PIN10
GPIO51/MOA#/SIN6
SIN6
PIN11
GPIO52/DRVA#/SOUT6
SOUT6
PIN12
GPIO53/WDATA#/DCD6#
DCD6#
PIN13
GPIO54/DIR#/RI6#
RI6#
PIN14
GPIO55/STEP#/CTS6#
CTS6#
PIN15
GPIO56/HDSEL#/DTR6#
DTR6#
PIN16
GPIO57/WGATE#/DSR6#
DSR6#
CONFIGURE REGISTER
INDEX 27H BIT3-2 = 00
INDEX 28H BIT1-0 = 01 ONLY SIN6/SOUT6
AVAILABLE
INDEX 28H BIT1-0 = 10 ONLY SIN6/SOUT6/RTS6#
AVAILABLE
INDEX 28H BIT1-0 = 11 FULL UART
7.3 FDC Device Configuration Registers (LDN CR00)
“-“ Reserved or Tri-State
Register 0x[HEX]
Register Name
30
FDC Device Enable Register
60
Base Address High Register
61
Base Address Low Register
70
IRQ Channel Select Register
74
DMA Channel Select Register
F0
FDD Mode Register
F2
FDD Drive Type Register
F4
FDD Selection Register
MSB
--
Default Value
LSB
-----
1
0000001
1
1111000
0
- - - - 011
0
- - - - - 01
0
- - - 0111
0
- - - - - -1
1
- - - 00 - 0
0
7.3.1FDC Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
- Reserved
0: disable FDC.
0
FDC_EN
R/W LRESET# 1
1: enable FDC.
Description
7.3.2Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W LRESET# 03h The MSB of FDC base address.
7.3.3Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W LRESET# F0h The LSB of FDC base address.
132
Jan, 2012
V0. 12P