F81866A Datasheet, PDF (118/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

7.1.6 Vendor ID Register ⎯ Index 24h
Bit
Name
R/W Reset Default
7-0
VENDOR_ID2
R
-
34h
F81866A
Description
Vendor ID 2.
7.1.7 I2C Address Select Register ⎯ Index 25h
Bit
Name
R/W Reset Default
Description
7-1
I2C_ADDR
R/W 5VSB
0 EN_ARA_MODE R/W 5VSB
I2C address is used to R/W hardware monitor registers.
0 ^{The default address is determined by I2C_ADDR power on strap pin.}
It could also be changed by writing this byte with the entry key 0x19,
0x34. The default value is 0x2E which indicates the address is 0x5C.
0: disable I2C ARA.
0
1: enable I2C ARA.
7.1.8 Clock Select Register ⎯ Index 26h
Bit
Name
R/W Reset Default
Description
The clock source of CLKIN.
00: CLKIN is 48MHz
7-6
CLK_SEL
R/W 5VSB 0 10: CLKIN is 24MHz
01: CLKIN is 14.318MHz.
10: Reserved.
5
Reserved
-
- Reserved.
4 MO_PIN_LVL_SEL R/W 5VSB
MCLK/MDATA input level select.
0 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 76 input level select.
3 PIN76_LVL_SEL R/W 5VSB 0 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 71 input level select.
2 PIN71_LVL_SEL R/W 5VSB 0 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 68 input level select.
1 PIN68_LVL_SEL R/W 5VSB 1 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 67 input level select.
0 PIN67_LVL_SEL R/W 5VSB 1 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
7.1.9 Port Select Register ⎯ Index 27h
Bit
Name
R/W Reset Default
Description
0: Force Mode.
1: Alarm Mode.
7
OVP_MODE
R/W VBAT* -
The default value is determined by power on strap.
*Trap value will reset by VBAT.
118
Jan, 2012
V0. 12P