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F81866A Datasheet, PDF (147/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power
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F81866A
7.7.4.9GPIO0 SMI Enable Register ⎯ Index F8h
Bit
Name
R/W Reset Default
Description
0: Disable SMI event.
7 GPIO07_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO07_SMI_ST is set.
0: Disable SMI event.
6 GPIO06_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO06_SMI_ST is set.
0: Disable SMI event.
5 GPIO05_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO05_SMI_ST is set.
0: Disable SMI event.
4 GPIO04_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO04_SMI_ST is set.
0: Disable SMI event.
3 GPIO03_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO03_SMI_ST is set.
0: Disable SMI event.
2 GPIO02_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO02_SMI_ST is set.
0: Disable SMI event.
1 GPIO01_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO01_SMI_ST is set.
0: Disable SMI event.
0 GPIO00_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO00_SMI_ST is set.
7.7.4.10GPIO0 SMI Status Register ⎯ Index F9h
Bit
Name
R/W Reset Default
Description
0: No SMI event.
7 GPIO07_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO07 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
6 GPIO06_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO06 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
5 GPIO05_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO05 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
4 GPIO04_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO04 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
3 GPIO03_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO03 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
2 GPIO02_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO02 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1 GPIO01_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO01 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
0 GPIO00_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO00 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
147
Jan, 2012
V0. 12P
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