F81866A Datasheet, PDF (177/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
5
RI1_WAKEUP_EN
R/W VBAT 0 Set this bit to enable RI1# event to wakeup system.
4
Reserved
R/W VBAT 0 Reserved
3
GP_WAKEUP_EN
R/W VBAT 0 Set this bit to enable GPIO event to wakeup system.
2 TMOUT_WAKEUP_EN R/W VBAT 0 Set this bit to enable Timeout event to wakeup system.
1
MO_WAKEUP_EN
R/W VBAT 0 Set this bit to enable Mouse event to wakeup system.
0
KB_WAKEUP_EN
R/W VBAT 0 Set this bit to enable Keyboard event to wakeup system.
7.9.23ERP Deep S3 Delay Register ⎯ Index E9h
Bit
Name
R/W _Reset Default
Description
7-0
DS3_DELAY_TIME
R/W VBAT Fh ^{The delay time from S3 state to deep S3 state. The unit is 64ms and}
default is 1.024 sec.
7.9.24ERP Mode Select Register ⎯ Index ECh
Bit
Name
R/W _Reset Default
Description
00: Fintek G3’ mode.
01: Intel DSW + Fintek G3` mode.
7-6
ERP_MODE
R/W VBAT 0
10: Reserved.
11: Intel DSW mode.
5
DPWROK_CTRL_EN R/W VBAT 0 Set “1” to enable DPWROK reset by ERP_CTRL1#.
0: disable ERP soft start.
4
SOFT_START_EN
R/W VBAT 1
1: enable ERP soft start.
The soft start rate.
00: 5ms.
3-2 SOFT_START_RATE R/W VBAT 1h 01: 10ms.
10: 27ms.
11: 54ms.
1-0
Reserved
-
-
- Reserved
7.9.25ERP WDT Control Register ⎯ Index EDh
Bit
Name
R/W _Reset Default
Description
7-6 ERP_WD_TIME[11:10] R/W _VBAT
Time of ERP watchdog timer.
-
Write index EEh will load watchdog time.
7-5
Reserved
R
-
4 ERP_WDTMOUT_STATUS R VBAT
3-2 ERP_WD_TIME[9:8] R/W VBAT
1
WD_UNIT
R/W VBAT
0
WD_EN
R/W VBAT
- Reserved
- Watchdog timeout status.
- Reserved
ERP WDT unit. It is the time unit of ERP_WD_TIME.
0 ^{0: 1sec.}
1: 60 sec.
0 Set “1” to enable ERP WDT. Auto clear if timeout occurred.
177
Jan, 2012
V0. 12P