F81866A Datasheet, PDF (49/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
TSI, I2C Temperature 2 Low Byte – Index E2h
Bit
Name
R/W Reset Default
Description
This is the low byte of Intel temperature interface CPU reading. The
reading is the fraction part of CPU temperature. Bit 0 indicates the error
TSI_TEMP2_LO
R 5VSB
status.
-
0: No error.
7-0
1: Error code.
To access this byte, MCH_BANK_SEL should be set to “0”.
This is the 12^th byte of the block read protocol.
I2C_DATA2
R/W 5VSB 8’h00 This byte is also used as the 3rd byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI, I2C Temperature 2 High Byte – Index E3h
Bit
Name
R/W Reset Default
Description
This is the high byte of Intel temperature interface CPU reading. The
TSI_TEMP2_HI
R 5VSB
- reading is the decimal part of CPU temperature.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 13^th byte of the block read protocol.
I2C_DATA3
R/W 5VSB 8’h00 This byte is also used as the 4th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI, I2C Temperature 3 – Index E4h
Bit
Name
R/W Reset Default
Description
TSI_TEMP3
R 5VSB
This is the high byte of Intel temperature interface MCH reading. The
- range is 0~255^ºC.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 14^th byte of the block read protocol.
I2C_DATA4
R/W 5VSB 8’h00 This byte is also used as the 5th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI, I2C Temperature 4 – Index E5h
Bit
Name
R/W Reset Default
Description
7-0
TSI_TEMP4
R 5VSB
This is the high byte of Intel temperature interface DIMM0 reading. The
- range is 0~255^ºC.
To access this byte, MCH_BANK_SEL should be set to “0”.
49
Jan, 2012
V0. 12P