F81866A Datasheet, PDF (138/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

Keyboard Mouse Swap.
0: Keyboard/Mouse is not swapped.
4
KB_MO_SWAP R/W VBAT 0
1: Keyboard/Mouse is swapped.
This bit could be programmed by user.
3-0 KBC_TEST_BIT R/W VBAT 3h Fintek test mode bits.
F81866A
7.7 GPIO Registers (CR06)
7.7.1.GPIO Configuration Registers
“-“ Reserved or Tri-State
Register
0x[HEX]
30
Register Name
GPIO Device Enable Register
60
Base Address High Register
61
Base Address Low Register
MSB
Default Value
LSB
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
7.7.1.1GPIO Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
- Reserved
0: disable GPIO I/O port.
0
GPIO_EN
R/W LRESET# 0
1: enable GPIO I/O port.
Description
7.7.1.2Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 GP_BASE_ADDR_HI R/W LRESET# 00h The MSB of GPIO I/O port address.
138
Jan, 2012
V0. 12P