F81866A Datasheet, PDF (159/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
0: Disable SMI event.
4 GPIO54_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO54_SMI_ST is set.
0: Disable SMI event.
3 GPIO53_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO53_SMI_ST is set.
0: Disable SMI event.
2 GPIO52_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO52_SMI_ST is set.
0: Disable SMI event.
1 GPIO51_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO51_SMI_ST is set.
0: Disable SMI event.
0 GPIO50_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO50_SMI_ST is set.
7.7.9.6GPIO5 SMI Status Register ⎯ Index A9h
Bit
Name
R/W Reset Default
Description
0: No SMI event.
7 GPIO57_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO57 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
6 GPIO56_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO56 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
5 GPIO55_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO55 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
4 GPIO54_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO54 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
3 GPIO53_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO53 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
2 GPIO52_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO52 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1 GPIO51_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO51 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
0 GPIO50_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO50 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
7.7.10.GPIO6x Configuration Registers
Register
0x[HEX]
Register Name
90
GPIO6 Output Enable Register
91
GPIO6 Output Data Register
92
GPIO6 Pin Status Register
MSB
0
0
1
1
-
-
Default Value
LSB
0
0
0
0
00
1
1
1
1
11
-
-
-
-
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159
Jan, 2012
V0. 12P