F81866A Datasheet, PDF (116/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

7. Register Description
F81866A
The configuration register is used to control the behavior of the corresponding devices. To configure the register,
using the index port to select the index and then writing data port to alter the parameters. The default index port and
data port are 0x4E and 0x4F respectively. Pull down the RTS1# pin to change the default value to 0x2E/0x2F. To
enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0xAA
to the index port. Following is an example to enable configuration and disable configuration by using debug.
-o 4e 87
-o 4e 87( enable configuration )
-o 4e aa( disable configuration )
The Following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of
all registers and their default value. Please refer to each device chapter if you want more detail information.
7.1 Global Control Registers
“-“ Reserved or Tri-State
Global Control Registers
Register
0x[HEX]
Register Name
MSB
Default Value
LSB
02
Software Reset Register
--
-
-
-
-
-
0
07
Logic Device Number Register (LDN)
00 0
0
0
0
0
0
20
Chip ID Register
00 0
1
0
0
0
0
21
Chip ID Register
00 0
1
0
0
0
0
23
Vendor ID Register
00 0
1
1
0
0
1
24
Vendor ID Register
00 1
1
0
1
0
0
25
I2C Address Register
00 0
0
0
0
0
0
26
Clock Select Register
00 -
0
0
0
1
1
27
Port Select Register
1/0 1/0 0 1/0 0
0
-
0
28
Multi Function Select 1 Register
28
Multi Function Select 2 Register
29
Multi Function Select 3 Register
-1 1
0
0
0
0
0
--
-
-
-
-
0
0
00 0
0
0
0
1
1
29
10Hz Clock Divisor High Byte
00 0
0
0
0
1
1
2A
10Hz Clock Divisor Low Byte
--
-
-
-
-
-
-
2A
10Hz Clock Divisor Low Byte
11 1
0
0
1
1
1
2B
Multi Function Select 4 Register
00 0
-
-
-
1
0
2B
10Hz Fine Tune Clock Count High Byte
-
-
-
-
-
-
-
-
116
Jan, 2012
V0. 12P