F81866A Datasheet, PDF (171/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

0 UART1_PME_EN R/W 5VSB
UART 1 PME event enable.
0 0: disable UART 1 PME event.
1: enable UART 1 PME event.
F81866A
7.9.5PME Event Status 2 Register ⎯ Index F3h
Bit
Name
R/W _Reset Default
Description
RI2# PME event status.
0: RI2# has no PME event.
7
RI2_PME_ST R/WC _5VSB
-
1: RI2# has a PME event to assert. Write 1 to clear to be ready for next PME
event.
RI1# PME event status.
0: RI1# has no PME event.
6
RI1_PME_ST R/WC _5VSB
-
1: RI1# has a PME event to assert. Write 1 to clear to be ready for next PME
event.
UART 6 PME event status.
5 UART6_PME_ST R/WC 5VSB
0: UART 6 has no PME event.
-
1: UART 6 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
UART 5 PME event status.
4 UART5_PME_ST R/WC 5VSB
0: UART 5 has no PME event.
-
1: UART 5 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
UART 4 PME event status.
3 UART4_PME_ST R/WC 5VSB
0: UART 4 has no PME event.
-
1: UART 4 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
UART 3 PME event status.
2 UART3_PME_ST R/WC 5VSB
0: UART 3 has no PME event.
-
1: UART 3 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
UART 2 PME event status.
1 UART2_PME_ST R/WC 5VSB
0: UART 2 has no PME event.
-
1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
171
Jan, 2012
V0. 12P