F81866A Datasheet, PDF (56/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

HWM Manual Control Status Register 2⎯ Index 52h
Bit
Name
R/W Reset Default
Description
7
5VSB_CONV_STS WC 5VSB - 5VSB voltage channel had finish converting
6 VBAT_CONV_STS WC 5VSB - VBAT voltage channel had finish converting
5 VSB3V_CONV_STS WC 5VSB - VSB3V voltage channel had finish converting
4 VIN4_CONV_STS WC 5VSB - VIN4 voltage channel had finish converting
3 VIN3_CONV_STS WC 5VSB - VIN3 voltage channel had finish converting
2 VIN2_CONV_STS WC 5VSB - VIN2 voltage channel had finish converting
1 VIN1_CONV_STS WC 5VSB - VIN1 voltage channel had finish converting
0
VCC_CONV_STS WC 5VSB - VCC voltage channel had finish converting
F81866A
HWM RAW Data Register 1⎯ Index 55h
Bit
Name
R/W Reset Default
Description
7-0
RAW_DATA_L
R 5VSB 0 Low byte of HM converting raw data
HWM RAW Data Register 2⎯ Index 56h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved
1-0
RAW_DATA_H
R 5VSB 0 The highest two bits of HM converting raw data
Temperature Register
Temperature PME# Enable Register ⎯ Index 60h
Bit
Name
R/W Reset Default
7
Reserved
R/W -
0 Reserved
Description
6 EN_ T2_OVT_PME R/W 5VSB
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT
0
setting.
5 EN_ T1_OVT_PME R/W 5VSB
4 EN_ T0_ OVT_PME R/W 5VSB
3
Reserved
R/W -
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT
0
setting.
If set this bit to 1, PME# signal will be issued when TEMP0 exceeds OVT
0 _setting.
0 Reserved
2 EN_ T2_EXC_PME R/W 5VSB
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high
0
limit setting.
1 EN_ T1_EXC_PME R/W 5VSB
0 EN_ T0_EXC_PME R/W 5VSB
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high
0
limit setting.
If set this bit to 1, PME# signal will be issued when TEMP0 exceeds high
0 _{limit setting.}
56
Jan, 2012
V0. 12P