F81866A Datasheet, PDF (149/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

0: GPIO12 outputs 0 when in output mode.
2
GPIO12_VAL R/W 5VSB 1
1: GPIO12 outputs 1 when in output mode.
0: GPIO11 outputs 0 when in output mode.
1
GPIO11_VAL
R/W 5VSB
1
1: GPIO11 outputs 1 when in output mode.
0: GPIO10 outputs 0 when in output mode.
0
GPIO10_VAL R/W 5VSB 1
1: GPIO10 outputs 1 when in output mode.
F81866A
7.7.5.3GPIO1 Pin Status Register ⎯ Index E2h (This byte could be also read by base address + 7)
Bit
Name
R/W Reset Default
Description
7
GPIO17_IN
R
-
- The pin status of PECI/GPIO17.
6
GPIO16_IN
R
-
- The pin status of BEEP/GPIO16/SDA.
5
GPIO15_IN
R
-
- The pin status of WDTRST#/GPIO15.
4
GPIO14_IN
R
-
- The pin status of GPIO14/AT_ATX_TRAP.
3
GPIO13_IN
R
-
- The pin status of SDA/GPIO13/IRRX.
2
GPIO12_IN
R
-
- The pin status of SCL/GPIO12/IRTX
1
GPIO11_IN
R
-
- The pin status of GPIO11/LED_VCC.
0
GPIO10_IN
R
-
- The pin status of GPIO10/LED_VSB.
7.7.5.4GPIO1 Drive Enable Register ⎯ Index E3h
Bit
Name
R/W Reset Default
Description
7 GPIO17_DRV_EN R/W 5VSB
0: GPIO17 is open drain in output mode.
0
1: GPIO17 is push pull in output mode.
6 GPIO16_DRV_EN R/W 5VSB
0: GPIO16 is open drain in output mode.
0
1: GPIO16 is push pull in output mode.
5 GPIO15_DRV_EN R/W 5VSB
0: GPIO15 is open drain in output mode.
0
1: GPIO15 is push pull in output mode.
4 GPIO14_DRV_EN R/W 5VSB
0: GPIO14 is open drain in output mode.
0
1: GPIO14 is push pull in output mode.
3 GPIO13_DRV_EN R/W 5VSB
0: GPIO13 is open drain in output mode.
0
1: GPIO13 is push pull in output mode.
2 GPIO12_DRV_EN R/W 5VSB
0: GPIO12 is open drain in output mode.
0
1: GPIO12 is push pull in output mode.
1 GPIO11_DRV_EN R/W VBAT
0: GPIO11 is open drain in output mode.
0 1: GPIO11 is push pull in output mode.
This bit is powered by VBAT.
0 GPIO10_DRV_EN R/W VBAT
0: GPIO10 is open drain in output mode.
0 1: GPIO10 is push pull in output mode.
This bit is powered by VBAT.
7.7.5.5GPIO1 SMI Enable Register ⎯ Index E8h
Bit
Name
R/W Reset Default
Description
0: Disable SMI event.
7 GPIO17_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO17_SMI_ST is set.
149
Jan, 2012
V0. 12P