F81866A Datasheet, PDF (191/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
IRQ_MODE1 and IRQ_MODE0 will select the UART5 interrupt mode if IRQ
sharing is enabled.
00 : Sharing IRQ active low Level mode.
1
IRQ_MODE0
R/W LRESET# 0 ^{01 : Sharing IRQ active high edge mode.}
10 : Sharing IRQ active high Level mode.
11 : Reserved.
This bit is effective at IRQ is sharing with the other device (IRQ_SHARE, bit 1).
0 : IRQ is not sharing with other device.
0
IRQ_SHARE
R/W LRESET# 0 _{1 : IRQ is sharing with other device.}
7.14.6Clock Register ⎯ Index F2h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved.
Select the clock source for UART5.
00: 1.8432MHz.
1-0 UART5_CLK_SEL R/W LRESET# 00b 01: 18.432MHz.
10: 24MHz.
11: 14.769MHz.
7.14.79bit-mode Slave Address Register ⎯ Index F4h
Bit
Name
R/W Reset Default
Description
This byte accompanying with SADEN will determine the given address and
broadcast address in 9-bit mode. The UART will response to both given and
broadcast address.
Following description determines the given address and broadcast address:
17. given address: If bit n of SADEN is “0”, then the corresponding bit of
SADDR is don’t care.
18. broadcast address: If bit n of ORed SADDR and SADEN is “0”, don’t care
7-0
SADDR
R/W LRESET# 00h
that bit. The remaining bit which is “1” is compared to the received
address.
Ex.
SADDR
0101_1100b
SADEN
1111_1001b
Given Address
0101_1xx0b
Broadcast Address
1111_11x1b
191
Jan, 2012
V0. 12P