F81866A Datasheet, PDF (14/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
Watch Dog Timer
¾ Time resolution minute/second
¾ Maximum 256 minutes or 256 seconds
¾ Output signal via WDTRST#/PWOK
¾ WDT could also wake up PME#, PSWOUT#
Power Saving Function
¾ G3-like Timing Control
¾ Comply With ERP Lot 6.0
¾ Built in Soft Start Function for Two Control Pins with VSB Power Sources Control.
¾ Event In via GPIO0x, GPIO1x, RI1#, and RI2#
Support Intel Cougar Point Timing (DSW)
UART
¾ Provide 6 fully functional UART
¾ 6 high-speed 16C550/16C650/16C750/16C850 compatible UARTs
¾ Provide auto flow control function
¾ Baud rate supports 115.2K, max. up to 1.5M
¾ Support IRQ 3,4,5,6,7,8,9,10,11 sharing
¾ Provide Multi drop (9-bits) Function for Gaming Machine
¾ Support IrDA version 1.0 SIR protocol (Multi with UART 6)
¾ Support Ring-In Wake Up via RI1# and RI2#
Infrared
¾ Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
(Multi with UART 6)
Provide ATX Emulates AT Function
Package
¾ 128-pin LQFP (14mm * 14mm) green package
Noted: Patented TW207103 TW207104 TW220442 US6788131 B1 TWI235231 TW237183
TWI263778
14
Jan, 2012
V0. 12P