F81866A Datasheet, PDF (80/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
FAN2 SEGMENT 3 SPEED COUNT Register – Index BCh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the FAN2_MODE (CR96)
2’b00: The value that set in this byte is the relative expect fan speed %
B2h
7-0
SEC3SPEED2
R/W 5VSB
of the full speed in this temperature section.
(70%)
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN2 SEGMENT 4 SPEED COUNT Register – Index BDh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the FAN2_MODE (CR96)
2’b00: The value that set in this byte is the relative expect fan speed %
99h
7-0
SEC4SPEED2
R/W 5VSB
of the full speed in this temperature section.
(60%)
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN2 SEGMENT 5 SPEED COUNT Register – Index BEh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the FAN2_MODE (CR96)
80h ^{2’b00: The value that set in this byte is the relative expect fan speed %}
7-0
SEC5PEED2
R/W 5VSB (50%) of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN2 Temperature Mapping Select – Index BFh
Bit
Name
R/W Reset Default
Description
FAN2_TEMP_
This bit companies with FAN2_TEMP_SEL to select the temperature
7
R/W 5VSB
0
SEL_DIG
source for controlling FAN2.
This bit and FREQ_SEL_ADD2 are used to select FAN2 PWM
frequency. NEW_FREQ_SEL2 = { FREQ_SEL_ADD2,
FAN2_PWM_FREQ_SEL}
FAN2_PWM_
6
R/W 5VSB
0 00: 23.5 KHz
FREQ_SEL
01: 11.75 KHz
10: 5.875 KHz
11: 220 Hz
5
FAN2_UP_T_EN R/W 5VSB
0 Set 1 to force FAN2 to full speed if any temperature over its high limit.
80
Jan, 2012
V0. 12P