F81866A Datasheet, PDF (66/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
FAN BEEP# Enable Register ⎯ Index 93h
Bit
Name
R/W Reset Default
Description
7
Reserved
-
-
- Reserved
FULL_WITH_
6
R/W 5VSB 0 Set one will enable FAN to force full speed when T2 over high limit.
T2_EN
FULL_WITH_
5
R/W 5VSB 0 Set one will enable FAN to force full speed when T1 over high limit.
T1_EN
4
Reserved
-
-
- Reserved
3
Reserved
-
-
- Reserved.
2 EN_FAN3_ BEEP R/W 5VSB 0 A one enables the corresponding interrupt status bit for BEEP.
1 EN_FAN2_ BEEP R/W 5VSB 0 A one enables the corresponding interrupt status bit for BEEP.
0 EN_FAN1_ BEEP R/W 5VSB 0 A one enables the corresponding interrupt status bit for BEEP.
FAN Type Select Register ⎯ Index 94h (FAN_PROG_SEL = 0)
Bit
Name
R/W Reset Default
Description
7-6
Reserved
-
-
- Reserved.
5-4
FAN3_TYPE
R/W 3VCC
00: Output PWM mode (push pull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal.
10: Output PWM mode (open drain) to control Intel 4-wire fans.
00
11: Reserved.
Bit 0 is power on trap by FANCTL3
0: FANCTL3 is pull up by external resistor.
1: FANCTL3 is pull down by internal 100K Ω resistor.
00: Output PWM mode (push pull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal.
3-2
FAN2_TYPE
R/W 3VCC
10: Output PWM mode (open drain) to control Intel 4-wire fans.
00
11: Reserved.
Bit 0 is power on trap by FANCTL2
0: FANCTL2 is pull up by external resistor.
1: FANCTL2 is pull down by internal 100K Ω resistor.
66
Jan, 2012
V0. 12P