F81866A Datasheet, PDF (94/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

Watchdog Timer Configuration Register 2 ⎯ base address + 06h
Bit
Name
R/W Reset Default
7-0
WD_TIME
R/W 5VSB 0 ^{Time of watchdog timer}
Description
F81866A
Watchdog PME Control Register ⎯ base address + 0Ah
Bit
Name
R/W Reset Default
Description
The PME Status.
7
WDT_PME
R 5VSB -- This bit will set when WDT_PME_EN is set and the watchdog timer is 1
unit before time out (or time out).
6
WDT_PME_EN R/W 5VSB
0
0: Disable Watchdog PME.
1: enable Watchdog PME.
5-1
Reserved
--
-- ^Reserved.
0
WDOUT_EN
R/W 5VSB
0
0: disable Watchdog time out output via WDTRST#.
1: enable Watchdog time out output via WDTRST#.
6.8 ACPI Function
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of
power in a computer. It lets computer manufacturer and user to determine the computer’s power usage
dynamically.
There are three ACPI states that are of primary concern to the system designer and they are
designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this state. The
other two are called sleep states and reflect different power consumption when power-down. S3 is a
state that the processor is powered down but the last procedural state is being stored in memory which is
still active. S5 is a state that memory is off and the last procedural state of the processor has been stored
to the hard disk. Take S3 and S5 as comparison, since memory is fast, the computer can quickly come
back to the full-power state, the disk is slower than the memory and the computer takes longer time to
come back to the full-power state. However, since the memory is off, S5 draws the minimal power
comparing to S0 and S3.
ACPI includes three sub items as below:
1. Power Control (Include wake up via sleep state, wake up stage detection, AC loss & resume
control methods)
2.Intel Power Saving Function (Deep Sleep Well, DSW: see next section for the detail)
3.EU Power Saving Function (EUP/ERP Command Lot 6.0: see next section for the detail)
Where item 2 & 3 could be coexisted via ERP_CTRL0# (follow SLP_SUS#) & ERP_CTRL1# (After
the system enters S3 1.024s & S5 6.4s, EUP/ERP mode could be achieved).
Before entering into the main section, let’s check out the related hardware control signal first.
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Jan, 2012
V0. 12P