F81866A Datasheet, PDF(88/210 Page) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

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F81866A Datasheet, PDF (88/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

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PS/2 wakeup function

F81866A

The KBC supports keyboard and mouse wakeup function. KBC will assert PME or PWSOUT#

signal. Those wakeup conditions are controlled by the configuration register.

6.6 GPIO

F81866A has 72 pins GPIO in total. All GPIO supports digit IO for Input/Output control, Output

data control, input status and High/Low Level/Pulse, Open Drain/Push Pull function selection. The

GPIO0x and GPIO1x support interrupt status. The GPIO0x, GPIO1x, GPIO5x, and GPIO8x have

different SIRQ channels. Please see 6.6.1 section for GPIO access methods and status:

6.6.1 GPIO Access Method

There are nine sets of GPIO in F81866A which can be accessed by three ways as below:

1. Configuration register port: Use 0x4E/0x4F (or 0x2E/0x2F) port with logic device number

0x06. Please refer to configuration register for detail.

2. Index/Data port: The index port is base address + 0 and data port is base address + 1. To

access the GPIO register, user should first write index to index port and then read/write

from/to data port. The index for each register is same as the definition in configuration

3. Digital I/O: This way could access GPIO data register only. It is used for quickly control the

GPIO pins. The register for each address is as list:

Offset

8h*

9h*

Ah*

B-Fh*

*Available when GPIO_DEC_RANGE is set â1â (Configuration register index 0x27, bit 5)

GPIO Digital I/O Registers

Index Port

Data Port

GPIO8 Data Port

GPIO7 Data Port

GPIO6 Data Port

GPIO5 Data Port

GPIO0 Data Port

GPIO1 Data Port

GPIO2 Data Port

GPIO3 Data Port

GPIO4 Data Port

Reserved

MSB

Default Value

1111

----

LSB

Jan, 2012

V0. 12P

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