F81866A Datasheet, PDF (117/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

2C
10Hz Fine Tune Clock Count Low Byte
2C
GPIO0 Enable Register
2C
GPIO1 Enable Register
2C
GPIO2 Enable Register
2D
Wakeup Control Register
F81866A
-
-
-
-
-
-
-
-
--
-
0
0
0
0
0
00 0
-
1
1
1
1
00 0
0
0
0
0
0
--
-
-
1
0
0
0
7.1.1 Software Reset Register ⎯ Index 02h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
- Reserved
0
SOFT_RST
W
-
- Write 1 to reset the register and device powered by VDD (VCC).
7.1.2 Logic Device Number Register (LDN) ⎯ Index 07h
Bit
Name
R/W Reset Default
Description
00h: Select FDC device configuration registers.
03h: Select Parallel Port device configuration registers.
04h: Select Hardware Monitor device configuration registers.
05h: Select KBC device configuration registers.
06h: Select GPIO device configuration registers.
07h: Select WDT device configuration registers.
0Ah: Select PME, ACPI and ERP device configuration registers.
7-0
LDN
R/W LRESET# 00h
10h: Select UART1 device configuration registers.
11h: Select UART2 device configuration registers.
12h: Select UART3 device configuration registers.
13h: Select UART4 device configuration registers.
14h: Select UART5 device configuration registers.
15h: Select UART6 device configuration registers.
Otherwise: Reserved.
7.1.3 Chip ID Register ⎯ Index 20h
Bit
Name
R/W Reset Default
7-0
CHIP_ID1
R
-
10h
Description
Chip ID 1.
7.1.4 Chip ID Register ⎯ Index 21h
Bit
Name
R/W Reset Default
7-0
CHIP_ID2
R
-
10h
Description
Chip ID2.
7.1.5 Vendor ID Register ⎯ Index 23h
Bit
Name
R/W Reset Default
7-0
VENDOR_ID1
R
-
19h
117
Description
Vendor ID 1.
Jan, 2012
V0. 12P