F81866A Datasheet, PDF (145/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
GPIO01 output mode select:
00: Level mode.
01: Inverted level mode.
3-2 GPIO01_MODE R/W 5VSB 00b
10: High pulse mode.
11: Low pulse mode.
The pulse width is determined by GPIO01_PW_SEL.
GPIO00 output mode select:
00: Level mode.
01: Inverted level mode.
1-0 GPIO00_MODE R/W 5VSB 00b
10: High pulse mode.
11: Low pulse mode.
The pulse width is determined by GPIO00_PW_SEL.
7.7.4.6GPIO0 Output Mode 2 Register ⎯ Index F5h
Bit
Name
R/W Reset Default
Description
GPIO07 output mode select:
00: Level mode.
01: Inverted level mode.
7-6 GPIO07_MODE R/W 5VSB 00b
10: High pulse mode.
11: Low pulse mode.
The pulse width is determined by GPIO07_PW_SEL.
GPIO06 output mode select:
00: Level mode.
01: Inverted level mode.
5-4 GPIO06_MODE R/w 5VSB 00b
10: High pulse mode.
11: Low pulse mode.
The pulse width is determined by GPIO06_PW_SEL.
GPIO05 output mode select:
00: Level mode.
01: Inverted level mode.
3-2 GPIO05_MODE R/W 5VSB 00b
10: High pulse mode.
11: Low pulse mode.
The pulse width is determined by GPIO05_PW_SEL.
GPIO04 output mode select:
00: Level mode.
01: Inverted level mode.
1-0 GPIO04_MODE R/W 5VSB 00b
10: High pulse mode.
11: Low pulse mode.
The pulse width is determined by GPIO04_PW_SEL.
145
Jan, 2012
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