F81866A Datasheet, PDF (93/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

6.6.2.8GPIO7x
Pin
Name
G3 -> S5
PIN STATUS
S0
S3
103 GPIO70
Z
user define
Z
104 GPIO71
Z
user define
Z
105 GPIO72
Z
user define
Z
106 GPIO73
Z
user define
Z
107 GPIO74
Z
user define
Z
108 GPIO75
Z
user define
Z
109 GPIO76
Z
user define
Z
110 GPIO77
Z
user define
Z
F81866A
S5
Register
Power
Well
Register
Reset Signal
Pin
Power
Well
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
6.6.2.9GPIO8x
Pin
Name
G3 -> S5
PIN STATUS
S0
S3
111 GPIO80
Z
user define
Z
112 GPIO81
Z
user define
Z
113 GPIO82
Z
user define
Z
114 GPIO83
Z
user define
Z
115 GPIO84
Z
user define
Z
116 GPIO85
Z
user define
Z
117 GPIO86
Z
user define
Z
118 GPIO88
Z
user define
Z
S5
Register
Power
Well
Register
Reset Signal
Pin
Power
Well
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
Z
I_VSB3V LRESET# 3VCC
6.7 Watchdog Timer Function
Watch dog timer is provided for system controlling. If time-out can trigger one signal to high/low level/pulse, the
signal is depend on register setting.
The time unit has two ways from 1sec or 60sec. In pulse mode, there are four pulse widths can be selected
(1ms/25ms/125ms/5sec). Others, please refer the device register description as below.
Watchdog Timer Configuration Register 1⎯ base address + 05h
Bit
Name
R/W Reset Default
Description
7
Reserved
R
-
0 ^Reserved
6
WDTMOUT_STS R/W 5VSB
0 ^{If watchdog timeout event occurred, this bit will be set to 1. Write a 1 to this}
bit will clear it to 0.
5
WD_EN
R/W 5VSB 0 ^{If this bit is set to 1, the counting of watchdog time is enabled.}
4
WD_PULSE
R/W 5VSB 0 ^{Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.}
3
WD_UNIT
R/W 5VSB 0 ^{Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit.}
2
WD_HACTIVE R/W 5VSB
0 ^{Select output polarity of RSTOUT# (1: high active, 0: low active) by setting}
this bit.
Select output pulse width of RSTOUT#
1-0 WD_PSWIDTH R/W 5VSB 0 0: 1 ms
1: 25 ms
2: 125 ms
3: 5 sec
93
Jan, 2012
V0. 12P