F81866A Datasheet, PDF (58/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
Temperature BEEP Enable Register ⎯ Index 63h
Bit
Name
R/W Reset Default
Description
7
Reserved
R/W -
0 Reserved
6 EN_ T2_ OVT_BEEP R/W 5VSB
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT
0
limit setting.
5 EN_ T1_ OVT_BEEP R/W 5VSB
4 EN_ T0_ OVT_BEEP R/W 5VSB
3
Reserved
R/W -
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT
0
limit setting.
0 ^{If set this bit to 1, BEEP signal will be issued when TEMP0 exceeds OVT}
limit setting.
0 Reserved
2 EN_ T2_EXC_BEEP R/W 5VSB
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high
0
limit setting.
1 EN_ T1_EXC_BEEP R/W 5VSB
0 EN_ T0_EXC_BEEP R/W 5VSB
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high
0
limit setting.
0 ^{If set this bit to 1, BEEP signal will be issued when TEMP0 exceeds high}
limit setting.
T1 OVT and High Limit Temperature Select Register ⎯ Index 64h
Bit
Name
R/W Reset Default
7-6
Reserved
R/W -
0 Reserved
Description
Select the source temperature for T1 OVT Limit.
0: Select T1 to be compared to Temperature 1 OVT Limit.
1: Select CPU temperature from PECI to be compared to Temperature 1
5-4 OVT_TEMP_SEL R/W 5VSB
OVT Limit.
0
2: Select CPU temperature from AMD TSI or Intel PCH I2C to be
compared to Temperature 1 OVT Limit.
3: Select the MAX temperature from Intel PCH I2C to be compared to
Temperature 1 OVT Limit.
3-2
Reserved
R/W -
0 Reserved
Select the source temperature for T1 High Limit.
0: Select T1 to be compared to Temperature 1 High Limit.
1: Select CPU temperature from PECI to be compared to Temperature 1
1-0 HIGH_ TEMP_SEL R/W 5VSB
High Limit.
0
2: Select CPU temperature from AMD TSI or Intel PCH I2C to be
compared to Temperature 1 High Limit.
3: Select the MAX temperature from Intel PCH I2C to be compared to
Temperature 1 High Limit.
58
Jan, 2012
V0. 12P