F81866A Datasheet, PDF (172/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

0 UART1_PME_ST R/WC 5VSB
F81866A
UART 1 PME event status.
0: UART 1 has no PME event.
-
1: UART 1 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
7.9.6ACPI Control Register 1 ⎯ Index F4h
Bit
Name
R/W Reset Default
Description
7-6
Reserved
-
-
- Reserved.
5 EN_GPWAKEUP R/W VBAT 0 Set one to enable GPIO SMI event asserted via PWSOUT#.
4 EN_KBWAKEUP R/W VBAT 0 Set one to enable keyboard wakeup event asserted via PWSOUT#.
3 EN_MOWAKEUP R/W VBAT 0 Set one to enable mouse wakeup event asserted via PWSOUT#.
The ACPI Control the PSON_N to always on or always off or keep last state
00 : keep last state
2-1
PWRCTRL
R/W VBAT 11 ^{10 : Always on}
01 : Bypass mode.
11: Always off
0 VSB_PWR_LOSS R/W 5VSB 1 ^{When 5VSB power lose, it will set to 1, and write 1 to clear it}
7.9.7ACPI Control Register 2 ⎯ Index F5h
Bit
Name
R/W Reset Default
Description
7
Reserved
-
-
- Reserved.
The additional PWOK delay.
00: no delay (default)
6-5 PWOK_DELAY R/W 5VSB 0 01: 100ms.
10: 200ms
11: 400ms.
The PWOK delay timing from VDD3VOK by followed setting
00 : 100ms
4-3
VDD_DELAY
R/W 5VSB 11 01 : 200ms
10 : 300ms
11 : 400ms (default)
2
VINDB_EN
R/W 5VSB 1 Enable the ATXPG de-bounce. (10us)
1-0
Reserved
-
-
- Reserved.
7.9.8ACPI Control Register 3 ⎯ Index F6h
Bit
Name
R/W Reset Default
Description
Select the KBC S3 condition source.
7
S3_SEL
R/W 5VSB 0 0: Enter S3 state when internal VDD3VOK signal de-asserted.
1: Enter S3 state when S3# is low or the TS3 register is set to 1.
6-5
Reserved
- 5VSB - Reserved.
0: PSON# is the inverted of S3# signal.
4
PSON_DEL_EN R/W 5VSB
0 1: PSON# will sink low only if the time after the last turn-off elapse at least 4
seconds.
3 WDT_PWOK_EN R/W 5VSB 0 Set “1” to this bit will enable WDT timeout event asset from PWOK pin.
2-0
Reserved
-
- Reserved.
172
Jan, 2012
V0. 12P