F81866A Datasheet, PDF (176/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
7.9.16ERP Control Register 2 ⎯ Index E2h
Bit
Name
R/W _Reset Default
Description
7
AC_LOST
R 5VSB 1 This bit is AC lost status and writes 1 to this bit will clear it.
6
Reserved
R/W VBAT 0 Reserved
0: Disable ERP_CTRL1# assert RSMRST low
5
VSB_CTRL_EN[1]
R/W VBAT 1’b0
1: Enable ERP_CTRL1# assert RSMRST low
0: Disable ERP_CTRL0# assert RSMRST low
4
VSB_CTRL_EN[0]
R/W VBAT 1’b0
1: Enable ERP_CTRL0# assert RSMRST low
3-2
Reserved
R/W VBAT 0 Reserved
Device detects 5VSB power ok (4.4V) and VSB3V_IN become high,
1
RSMRST_DET_5V_N R/W VBAT 0 and after ~50ms de-bounce time RSMRST will become high. But when
user set this bit to 1. RSMRST will not check 5VSB power ok.
0
Reserved
R
-
- Reserved
7.9.17ERP PWSIN De-bounce Register ⎯ Index E3h
Bit
Name
R/W ^Reset Default
Description
7-0
PWSIN_DEB_TIME
R/W VBAT 13h PWSIN# pin input de-bounce time. The unit is 1ms, default is 20ms.
7.9.18ERP RSMRST De-bounce Register ⎯ Index E4h
Bit
Name
R/W _Reset Default
Description
7-0
RSMRST_DEB_TIME R/W VBAT
9h
RSMRST internal de-bounce time. The unit is 1ms and default is
10ms.
7.9.19ERP PWSOUT Pulse Width Register ⎯ Index E5h
Bit
Name
R/W _Reset Default
Description
7-0
PWSOUT_PW
R/W VBAT C7h PWSOUT output pulse width. The unit is 1ms and default is 200ms.
7.9.20ERP PWSIN De-bounce Register ⎯ Index E6h
Bit
Name
R/W _Reset Default
Description
7-0
PSON_DEB_TIME
R/W VBAT 13h PSON# pin input de-bounce time. The unit is 1ms, default is 10ms.
7.9.21ERP Deep S5 Delay Register ⎯ Index E7h
Bit
Name
R/W _Reset Default
Description
7-0
DS5_DELAY_TIME
R/W VBAT
63h
The delay time from S5 state to deep S5 state. The unit is 64ms and
default is 6.4 sec.
7.9.22ERP Wakeup Enable Register ⎯ Index E8h
Bit
Name
R/W _Reset Default
Description
7
RI2_WAKEUP_EN
R/W VBAT 0 Set this bit to enable RI2# event to wakeup system.
6
Reserved
-
-
- Reserved
176
Jan, 2012
V0. 12P