F81866A Datasheet, PDF (178/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

7.9.26ERP WDT Time Register ⎯ Index EEh
Bit
Name
R/W ^Reset Default
Description
7-0
ERP_WD_TIME
R/W VBAT 0 Time of ERP watchdog timer.
F81866A
7.10 UART1 Device Configuration Registers (LDN CR10)
“-“ Reserved or Tri-State
Register 0x[HEX]
Register Name
30
Device Enable Register
60
Base Address High Register
61
Base Address Low Register
70
IRQ Channel Select Register
F0
IRQ Share Register
F2
Clock Select Register
F4
9bit-mode Slave Address Register
F5
9bit-mode Slave Address Mask Register
F6
FIFO Mode Register
MSB
--
00
11
--
00
--
00
00
00
Default Value
----
0000
1110
- - 01
00 - -
----
0000
0000
000 -
LSB
-1
11
00
00
00
00
00
00
00
7.10.1UART 1 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
- Reserved
0: disable UART 1 I/O Port.
0
UART 1_EN
R/W LRESET# 1
1: enable UART 1 I/O Port.
Description
7.10.2Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W LRESET# 03h The MSB of UART 1 base address.
7.10.3Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W LRESET# F8h The LSB of UART 1 base address.
7.10.4IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0
SELUR1IRQ
R/W LRESET# 4h Select the IRQ channel for UART 1.
178
Jan, 2012
V0. 12P