F81866A Datasheet, PDF (81/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

FAN2_
4
R/W 5VSB
INTERPOLATION_EN
FAN2_JUMP_
3
R/W 5VSB
HIGH_EN
FAN2_JUMP_
2
R/W 5VSB
LOW_EN
1-0 FAN2_TEMP_SEL R/W 5VSB
F81866A
1 Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN2 duty movement when temperature over
highest boundary.
0: The FAN2 duty will increases with the slope selected by
1 FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC1SPEED2
register.
This bit only activates in duty mode.
This register controls the FAN2 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN2 duty will decreases with the slope selected by
1 FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC2SPEED2
register.
This bit only activates in duty mode.
This registers companying with FAN2_TEMP_SEL_DIG select the
temperature source for controlling FAN2. The following value is
comprised by {FAN2_TEMP_SEL_DIG, FAN2_TEMP_SEL}
000: fan2 follows PECI temperature (CR7Eh)
001: fan2 follows temperature 1 (CR72h).
010: fan2 follows temperature 2 (CR74h).
10
011: fan2 follows temperature 0 (CR70h).
100: fan2 follows IBEX/TSI CPU temperature (CR7Ah)
101: fan2 follows IBEX PCH temperature (CR7Bh).
110: fan2 follows IBEX MCH temperature (CR7Ch).
111: fan2 follows IBEX maximum temperature (CR7Dh).
Otherwise: reserved.
C. FAN3 Index C0h- CFh
Address
Attribute
Reset
C0h
RO
3VCC
C1h
RO
3VCC
Default Value
Description
FAN3 count reading (MSB). At the moment of reading this
8’h0F
register, the LSB will be latched. This will prevent from data
updating when reading. To read the fan count correctly, read
MSB first and followed read the LSB.
8’hff
FAN3 count reading (LSB).
81
Jan, 2012
V0. 12P