F81866A Datasheet, PDF (155/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

7.7.8.1GPIO4 Output Enable Register ⎯ Index B0h
Bit
Name
R/W Reset Default
0: GPIO47 is input.
7
GPIO47_OE
R/W LRESET# 0
1: GPIO47 is output.
0: GPIO46 is input.
6
GPIO46_OE
R/W LRESET# 0
1: GPIO46 is output.
0: GPIO45 is input.
5
GPIO45_OE
R/W LRESET# 0
1: GPIO45 is output.
0: GPIO44 is input.
4
GPIO44_OE
R/W LRESET# 0
1: GPIO44 is output.
0: GPIO43 is input.
3
GPIO43_OE
R/W LRESET# 0
1: GPIO43 is output.
0: GPIO42 is input.
2
GPIO42_OE
R/W LRESET# 0
1: GPIO42 is output.
0: GPIO41 is input.
1
GPIO41_OE
R/W LRESET# 0
1: GPIO41 is output.
0: GPIO40 is input.
0
GPIO40_OE
R/W LRESET# 0
1: GPIO40 is output.
Description
F81866A
7.7.8.2GPIO4 Output Data Register ⎯ Index B1h (This byte could be also written by base address + 10 if
GPIO_DEC_RANGE is set to “1”)
Bit
Name
R/W Reset Default
Description
0: GPIO47 outputs 0 when in output mode.
7
GPIO47_DATA R/W LRESET# 1
1: GPIO47 outputs 1 when in output mode.
0: GPIO46 outputs 0 when in output mode.
6
GPIO46_DATA R/W LRESET# 1
1: GPIO46 outputs 1 when in output mode.
0: GPIO45 outputs 0 when in output mode.
5
GPIO45_DATA R/W LRESET# 1
1: GPIO45 outputs 1 when in output mode.
0: GPIO44 outputs 0 when in output mode.
4
GPIO44_DATA R/W LRESET# 1
1: GPIO44 outputs 1 when in output mode.
0: GPIO43 outputs 0 when in output mode.
3
GPIO43_DATA R/W LRESET# 1
1: GPIO43 outputs 1 when in output mode.
0: GPIO42 outputs 0 when in output mode.
2
GPIO42_DATA R/W LRESET# 1
1: GPIO42 outputs 1 when in output mode.
0: GPIO41 outputs 0 when in output mode.
1
GPIO41_DATA R/W LRESET# 1
1: GPIO41 outputs 1 when in output mode.
0: GPIO40 outputs 0 when in output mode.
0
GPIO40_DATA R/W LRESET# 1
1: GPIO40 outputs 1 when in output mode.
7.7.8.3GPIO4 Pin Status Register ⎯ Index B2h (This byte could be also read by base address + 10 if
GPIO_DEC_RANGE is set to “1”)
Bit
Name
R/W Reset Default
Description
7
GPIO47_ST
R
-
- The pin status of SIN4/GPIO47.
6
GPIO46_ST
R
-
- The pin status of SOUT4/GPIO46.
155
Jan, 2012
V0. 12P