F81866A Datasheet, PDF (173/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power

F81866A
7.9.9LED Control Register 1 ⎯ Index F8h
Bit
Name
R/W _Reset Default
Description
7 _{LED_VCC_INV_DIS R/W VBAT}
6
LED_VCC_DS3 R/W VBAT
5-4 _{LED_VCC_S5_MODE R/W VBAT}
3-2 _{LED_VCC_S3_MODE R/W VBAT}
1-0 _{LED_VCC_S0_MODE R/W VBAT}
0: LED_VCC clock output is inverted.
0
1: LED_VCC clock output is not inverted.
0: Disable LED_VCC deep S3 mode.
0
1: Enable LED_VCC deep S3 mode. Output 75% duty 0.25HZ clock.
The three bits {LED_VCC_S5_MODE_ADD, LED_VCC_S5_MODE [1:0]}
select the LED_VCC mode in S5 state.
000: Sink low.
001: Tri-state or drive high control by GPIO11_DRV_EN.
010: 0.5Hz clock with 50% duty.
011: 1Hz clock with 50% duty.
00
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
*When LED_VCC_INV_DIS is set to “1” the duty is 25%, otherwise, the duty
is 75%.
The three bits {LED_VCC_S3_MODE_ADD, LED_VCC_S3_MODE [1:0]}
select the LED_VCC mode in S3 state.
000: Sink low.
001: Tri-state or drive high control by GPIO11_DRV_EN.
010: 0.5Hz clock with 50% duty.
011: 1Hz clock with 50% duty.
00
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
*When LED_VCC_INV_DIS is set to “1” the duty is 25%, otherwise, the duty
is 75%.
The three bits {LED_VCC_S0_MODE_ADD, LED_VCC_S0_MODE [1:0]}
select the LED_VCC mode in S0 state.
000: Sink low.
001: Tri-state or drive high control by GPIO11_DRV_EN.
010: 0.5Hz clock with 50% duty.
011: 1Hz clock with 50% duty.
00
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
*When LED_VCC_INV_DIS is set to “1” the duty is 25%, otherwise, the duty
is 75%.
7.9.10LED Control Register 2 ⎯ Index F9h
Bit
Name
R/W ^Reset Default
7
Reserved
-
-
- Reserved
Description
173
Jan, 2012
V0. 12P