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F81866A Datasheet, PDF (23/210 Pages) Feature Integration Technology Inc. – 6 UARTs Super IO With 128 Bytes FIFO and Power
F81866A
MDATA
I/OD16st,5V
PS/2 Mouse Data.
61
SCL
I_VSB3V
Ilv/OD16st, 5v
I2C Interface CLOCK pin. Clock output for AMD
TSI & Intel PCH (IBX Peak).
MCLK
I/OD16st,5V
PS/2 Mouse Clock.
62
SDA
Ilv/OD16st, 5v I_VSB3V
I2C Interface DATA pin. AMD TSI & Intel PCH (IBX
Peak) data pin.
5.8 ACPI, ERP, SIR & GPIO
Pin
Pin Name
Type
PWR
Description
Standby power rail control pin 0. This pin controls an
external PMOS to turn on or off the standby power
ERP_CTRL0#
52
OD12,5V
I_VSB3V rail.
In the S5 state, the default is set to 1 to cut off the
standby power rail.
GPIO00
I/OOD12st,5v
General purpose IO.
Standby power rail control pin 1. This pin controls an
external PMOS to turn on or off the standby power
ERP_CTRL1#
53
OD12,5V
I_VSB3V rail.
In the S5 state, the default is set to 1 to cut off the
standby power rail.
GPIO01
I/OOD12st,5v
General purpose IO.
This pin asserts low when the PCH is planning to
SUS_WARN#
54
enter the DSW power state. It can detect 5VDUAL
INst
I_VSB3V level with delay setting supported. The delay time is
1ms~8S (default 4s)
GPIO02
I/OOD12st,5v
General purpose IO.
SUS_ACK#
55
OD12,5v
This pin must wait SUSWARN# signal for entering
I_VSB3V DSW power state.
GPIO03
I/OOD12st,5v
General purpose IO.
This pin asserts low which comes from PCH to shut
SLP_SUS#
56
INst,lv
off suspend power rails externally to enhance power
I_VSB3V saving function.
GPIO04
I/OOD12st,5v
General purpose IO.
GPIO05
I/OOD12st,5v
General purpose IO.
57
SOUT5
I_VSB3V UART Serial Output. Used to transmit serial data out to
O12
the communication link.
GPIO06
I/OOD12st,5v
General purpose IO.
58
SIN5
INt,5v
I_VSB3V UART Serial Input. Used to receive serial data
through the communication link.
GPIO07
I/OOD12st,5v
General purpose IO.
59
RTS5#
UART Request To Send. An active low signal informs
I_VSB3V
O12
the modem or data set that the controller is ready to
send data.
65
GPIO10
I/OOD12st,5v I_VSB3V General purpose IO.
23
Jan, 2012
V0. 12P